diff -r e4701d594b31 -r af1501668402 configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py	Wed Apr 27 10:30:27 2011 -0700
+++ b/configs/ruby/Ruby.py	Wed Apr 27 10:34:03 2011 -0700
@@ -87,8 +87,8 @@
         class RouterClass(GarnetRouter): pass
     else:
         class NetworkClass(SimpleNetwork): pass
-        class IntLinkClass(BasicIntLink): pass
-        class ExtLinkClass(BasicExtLink): pass
+        class IntLinkClass(SimpleIntLink): pass
+        class ExtLinkClass(SimpleExtLink): pass
         class RouterClass(BasicRouter): pass
     
     #
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/BasicLink.hh
--- a/src/mem/ruby/network/BasicLink.hh	Wed Apr 27 10:30:27 2011 -0700
+++ b/src/mem/ruby/network/BasicLink.hh	Wed Apr 27 10:34:03 2011 -0700
@@ -53,7 +53,7 @@
     void print(std::ostream& out) const;
 
     int m_latency;
-    int m_bw_multiplier;
+    int m_bandwidth_factor;
     int m_weight;
 };
 
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/BasicLink.cc
--- a/src/mem/ruby/network/BasicLink.cc	Wed Apr 27 10:30:27 2011 -0700
+++ b/src/mem/ruby/network/BasicLink.cc	Wed Apr 27 10:34:03 2011 -0700
@@ -32,7 +32,7 @@
     : SimObject(p)
 {
     m_latency = p->latency;
-    m_bw_multiplier = p->bw_multiplier;
+    m_bandwidth_factor = p->bandwidth_factor;
     m_weight = p->weight;
 }
 
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/BasicLink.py
--- a/src/mem/ruby/network/BasicLink.py	Wed Apr 27 10:30:27 2011 -0700
+++ b/src/mem/ruby/network/BasicLink.py	Wed Apr 27 10:34:03 2011 -0700
@@ -34,17 +34,21 @@
     type = 'BasicLink'
     link_id = Param.Int("ID in relation to other links")
     latency = Param.Int(1, "latency")
-    bw_multiplier = Param.Int("simple network bw constant, usually in bytes")
+    # The following banwidth factor does not translate to the same value for
+    # both the simple and Garnet models.  For the most part, the bandwidth
+    # factor is the width of the link in bytes, expect for certain situations
+    # with regard to the simple network.
+    bandwidth_factor = Param.Int("generic bandwidth factor, usually in bytes")
     weight = Param.Int(1, "used to restrict routing in shortest path analysis")
 
 class BasicExtLink(BasicLink):
     type = 'BasicExtLink'
     ext_node = Param.RubyController("External node")
     int_node = Param.BasicRouter("ID of internal node")
-    bw_multiplier = 64
+    bandwidth_factor = 64
 
 class BasicIntLink(BasicLink):
     type = 'BasicIntLink'
     node_a = Param.BasicRouter("Router on one end")
     node_b = Param.BasicRouter("Router on other end")
-    bw_multiplier = 16
+    bandwidth_factor = 16
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py	Wed Apr 27 10:30:27 2011 -0700
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py	Wed Apr 27 10:34:03 2011 -0700
@@ -41,7 +41,8 @@
                               "virtual channels per message class")
     virt_nets = Param.Int(Parent.number_of_virtual_networks,
                           "number of virtual networks")
-    channel_width = Param.Int(Parent.flit_size, "channel width == flit size")
+    channel_width = Param.Int(Parent.bandwidth_factor,
+                              "channel width == bw factor")
 
 class CreditLink_d(NetworkLink_d):
     type = 'CreditLink_d'
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/simple/SConscript
--- a/src/mem/ruby/network/simple/SConscript	Wed Apr 27 10:30:27 2011 -0700
+++ b/src/mem/ruby/network/simple/SConscript	Wed Apr 27 10:34:03 2011 -0700
@@ -33,9 +33,11 @@
 if not env['RUBY']:
     Return()
 
+SimObject('SimpleLink.py')
 SimObject('SimpleNetwork.py')
 
 Source('PerfectSwitch.cc')
+Source('SimpleLink.cc')
 Source('SimpleNetwork.cc')
 Source('Switch.cc')
 Source('Throttle.cc')
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/simple/SimpleLink.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/network/simple/SimpleLink.hh	Wed Apr 27 10:34:03 2011 -0700
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
+#define __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
+
+#include <iostream>
+#include <string>
+#include <vector>
+
+#include "params/SimpleExtLink.hh"
+#include "params/SimpleIntLink.hh"
+#include "mem/ruby/network/BasicLink.hh"
+
+class SimpleExtLink : public BasicExtLink
+{
+  public:
+    typedef SimpleExtLinkParams Params;
+    SimpleExtLink(const Params *p);
+    const Params *params() const { return (const Params *)_params; }
+
+    friend class Topology;
+    void print(std::ostream& out) const;
+
+    int m_bw_multiplier;
+};
+
+inline std::ostream&
+operator<<(std::ostream& out, const SimpleExtLink& obj)
+{
+    obj.print(out);
+    out << std::flush;
+    return out;
+}
+
+class SimpleIntLink : public BasicIntLink
+{
+  public:
+    typedef SimpleIntLinkParams Params;
+    SimpleIntLink(const Params *p);
+    const Params *params() const { return (const Params *)_params; }
+
+    friend class Topology;
+    void print(std::ostream& out) const;
+
+    int m_bw_multiplier;
+};
+
+inline std::ostream&
+operator<<(std::ostream& out, const SimpleIntLink& obj)
+{
+    obj.print(out);
+    out << std::flush;
+    return out;
+}
+
+#endif // __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/simple/SimpleLink.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/network/simple/SimpleLink.cc	Wed Apr 27 10:34:03 2011 -0700
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/ruby/network/simple/SimpleLink.hh"
+
+SimpleExtLink::SimpleExtLink(const Params *p)
+    : BasicExtLink(p)
+{
+    // For the simple links, the bandwidth factor translates to the
+    // bandwidth multiplier.  The multipiler, in combination with the 
+    // endpoint bandwidth multiplier - message size multiplier ratio, 
+    // determines the link bandwidth in bytes 
+    m_bw_multiplier = p->bandwidth_factor;
+}
+
+void
+SimpleExtLink::print(std::ostream& out) const
+{
+    out << name();
+}
+
+SimpleExtLink *
+SimpleExtLinkParams::create()
+{
+    return new SimpleExtLink(this);
+}
+
+SimpleIntLink::SimpleIntLink(const Params *p)
+    : BasicIntLink(p)
+{
+    // For the simple links, the bandwidth factor translates to the
+    // bandwidth multiplier.  The multipiler, in combination with the 
+    // endpoint bandwidth multiplier - message size multiplier ratio, 
+    // determines the link bandwidth in bytes 
+    m_bw_multiplier = p->bandwidth_factor;
+}
+
+void
+SimpleIntLink::print(std::ostream& out) const
+{
+    out << name();
+}
+
+SimpleIntLink *
+SimpleIntLinkParams::create()
+{
+    return new SimpleIntLink(this);
+}
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/simple/SimpleLink.py
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/ruby/network/simple/SimpleLink.py	Wed Apr 27 10:34:03 2011 -0700
@@ -0,0 +1,39 @@
+# Copyright (c) 2011 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Brad Beckmann
+
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import SimObject
+from BasicLink import BasicIntLink, BasicExtLink
+
+class SimpleExtLink(BasicExtLink):
+    type = 'SimpleExtLink'
+
+class SimpleIntLink(BasicIntLink):
+    type = 'SimpleIntLink'
diff -r e4701d594b31 -r af1501668402 src/mem/ruby/network/simple/SimpleNetwork.cc
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc	Wed Apr 27 10:30:27 2011 -0700
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc	Wed Apr 27 10:34:03 2011 -0700
@@ -36,6 +36,7 @@
 #include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/ruby/network/BasicLink.hh"
+#include "mem/ruby/network/simple/SimpleLink.hh"
 #include "mem/ruby/network/simple/SimpleNetwork.hh"
 #include "mem/ruby/network/simple/Switch.hh"
 #include "mem/ruby/network/simple/Throttle.hh"
@@ -148,10 +149,12 @@
         return;
     }
 
+    SimpleExtLink *simple_link = safe_cast<SimpleExtLink*>(link);
+
     m_switch_ptr_vector[src]->addOutPort(m_fromNetQueues[dest],
                                          routing_table_entry,
-                                         link->m_latency,
-                                         link->m_bw_multiplier);
+                                         simple_link->m_latency,
+                                         simple_link->m_bw_multiplier);
 
     m_endpoint_switches[dest] = m_switch_ptr_vector[src];
 }
@@ -198,10 +201,12 @@
         m_buffers_to_free.push_back(buffer_ptr);
     }
     // Connect it to the two switches
+    SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
+
     m_switch_ptr_vector[dest]->addInPort(queues);
     m_switch_ptr_vector[src]->addOutPort(queues, routing_table_entry,
-                                         link->m_latency, 
-                                         link->m_bw_multiplier);
+                                         simple_link->m_latency, 
+                                         simple_link->m_bw_multiplier);
 }
 
 void