diff -r e23be4d48994 -r 55322c8b548b src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh	Mon May 02 17:20:32 2011 -0500
+++ b/src/cpu/simple/base.hh	Mon May 02 17:21:17 2011 -0500
@@ -124,6 +124,7 @@
     enum Status {
         Idle,
         Running,
+        Faulting,
         ITBWaitResponse,
         IcacheRetry,
         IcacheWaitResponse,
diff -r e23be4d48994 -r 55322c8b548b src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Mon May 02 17:20:32 2011 -0500
+++ b/src/cpu/simple/timing.cc	Mon May 02 17:21:17 2011 -0500
@@ -725,6 +725,7 @@
     bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
 
     if (needToFetch) {
+        _status = Running;
         Request *ifetch_req = new Request();
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         setupFetchRequest(ifetch_req);
@@ -771,7 +772,22 @@
 void
 TimingSimpleCPU::advanceInst(Fault fault)
 {
-    if (fault != NoFault || !stayAtPC)
+
+    if (_status == Faulting)
+        return;
+
+    if (fault != NoFault) {
+        advancePC(fault);
+        if (fetchEvent.scheduled())
+            deschedule(fetchEvent);
+        DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
+        schedule(fetchEvent, nextCycle());
+        _status = Faulting;
+        return;
+    }
+
+
+    if (!stayAtPC)
         advancePC(fault);
 
     if (_status == Running) {
@@ -786,8 +802,6 @@
 void
 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 {
-    DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
-
     // received a response from the icache: execute the received
     // instruction
 
@@ -878,8 +892,7 @@
             tickEvent.schedule(pkt, next_tick);
 
         return true;
-    }
-    else if (pkt->wasNacked()) {
+    } else if (pkt->wasNacked()) {
         assert(cpu->_status == IcacheWaitResponse);
         pkt->reinitNacked();
         if (!sendTiming(pkt)) {