diff -r 02508707978d -r 642c46ec6201 src/arch/arm/faults.cc --- a/src/arch/arm/faults.cc Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/faults.cc Wed May 04 20:41:48 2011 -0500 @@ -108,7 +108,6 @@ CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | tc->readIntReg(INTREG_CONDCODES_F) | - tc->readIntReg(INTREG_CONDCODES_Q) | tc->readIntReg(INTREG_CONDCODES_GE); Addr curPc M5_VAR_USED = tc->pcState().pc(); ITSTATE it = tc->pcState().itstate(); diff -r 02508707978d -r 642c46ec6201 src/arch/arm/intregs.hh --- a/src/arch/arm/intregs.hh Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/intregs.hh Wed May 04 20:41:48 2011 -0500 @@ -113,7 +113,6 @@ INTREG_UREG1, INTREG_UREG2, INTREG_CONDCODES_F, - INTREG_CONDCODES_Q, INTREG_CONDCODES_GE, INTREG_FPCONDCODES, diff -r 02508707978d -r 642c46ec6201 src/arch/arm/isa.cc --- a/src/arch/arm/isa.cc Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/isa.cc Wed May 04 20:41:48 2011 -0500 @@ -216,6 +216,8 @@ warn("Not doing anything for read to miscreg %s\n", miscRegName[misc_reg]); break; + case MISCREG_CPSR_Q: + panic("shouldn't be reading this register seperately\n"); case MISCREG_FPSCR_QC: return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; case MISCREG_FPSCR_EXC: @@ -316,6 +318,13 @@ (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); } break; + case MISCREG_CPSR_Q: + { + assert(!(newVal & ~CpsrMaskQ)); + newVal = miscRegs[MISCREG_CPSR] | newVal; + misc_reg = MISCREG_CPSR; + } + break; case MISCREG_FPSCR_QC: { newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); diff -r 02508707978d -r 642c46ec6201 src/arch/arm/isa/insts/data.isa --- a/src/arch/arm/isa/insts/data.isa Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/isa/insts/data.isa Wed May 04 20:41:48 2011 -0500 @@ -48,7 +48,7 @@ ''' calcQCode = ''' - CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); + CpsrQ = (resTemp & 1) << 27; ''' calcCcCode = ''' @@ -239,11 +239,10 @@ code += ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; NextThumb = ((CPSR)newCpsr).t; NextJazelle = ((CPSR)newCpsr).j; diff -r 02508707978d -r 642c46ec6201 src/arch/arm/isa/insts/ldr.isa --- a/src/arch/arm/isa/insts/ldr.isa Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/isa/insts/ldr.isa Wed May 04 20:41:48 2011 -0500 @@ -106,7 +106,7 @@ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - URc = cpsr | CondCodesF | CondCodesQ | CondCodesGE; + URc = cpsr | CondCodesF | CondCodesGE; URa = cSwap(Mem.ud, cpsr.e); URb = cSwap(Mem.ud >> 32, cpsr.e); ''' diff -r 02508707978d -r 642c46ec6201 src/arch/arm/isa/insts/macromem.isa --- a/src/arch/arm/isa/insts/macromem.isa Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/isa/insts/macromem.isa Wed May 04 20:41:48 2011 -0500 @@ -90,11 +90,10 @@ CPSR cpsr = Cpsr; SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE, + cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) @@ -635,7 +634,6 @@ NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' diff -r 02508707978d -r 642c46ec6201 src/arch/arm/isa/insts/misc.isa --- a/src/arch/arm/isa/insts/misc.isa Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/isa/insts/misc.isa Wed May 04 20:41:48 2011 -0500 @@ -61,7 +61,7 @@ header_output = decoder_output = exec_output = "" mrsCpsrCode = ''' - Dest = (Cpsr | CondCodesF | CondCodesQ | CondCodesGE) & 0xF8FF03DF + Dest = (Cpsr | CondCodesF | CondCodesGE) & 0xF8FF03DF ''' mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", @@ -84,11 +84,10 @@ msrCpsrRegCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, Op1, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Op1, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", @@ -111,11 +110,10 @@ msrCpsrImmCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, imm, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", @@ -205,9 +203,7 @@ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (satInt(res, operand, imm)) - CondCodesQ = CondCodesQ | (1 << 27); - else - CondCodesQ = CondCodesQ; + CpsrQ = 1 << 27; Dest = res; ''' ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", @@ -221,9 +217,7 @@ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (uSatInt(res, operand, imm)) - CondCodesQ = CondCodesQ | (1 << 27); - else - CondCodesQ = CondCodesQ; + CpsrQ = 1 << 27; Dest = res; ''' usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", @@ -236,14 +230,13 @@ ssat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (satInt(res, argLow, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 15, 0, res); if (satInt(res, argHigh, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' @@ -257,14 +250,13 @@ usat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (uSatInt(res, argLow, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 15, 0, res); if (uSatInt(res, argHigh, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' diff -r 02508707978d -r 642c46ec6201 src/arch/arm/isa/insts/mult.isa --- a/src/arch/arm/isa/insts/mult.isa Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/isa/insts/mult.isa Wed May 04 20:41:48 2011 -0500 @@ -44,7 +44,7 @@ exec_output = "" calcQCode = ''' - CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); + CpsrQ = (resTemp & 1) << 27; ''' calcCcCode = ''' diff -r 02508707978d -r 642c46ec6201 src/arch/arm/isa/operands.isa --- a/src/arch/arm/isa/operands.isa Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/isa/operands.isa Wed May 04 20:41:48 2011 -0500 @@ -157,7 +157,6 @@ #Pseudo integer condition code registers 'CondCodesF': intRegCC('INTREG_CONDCODES_F'), - 'CondCodesQ': intRegCC('INTREG_CONDCODES_Q'), 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), 'OptCondCodesF': intRegCC( '''(condCode == COND_AL || condCode == COND_UC) ? @@ -219,6 +218,7 @@ #Fixed index control regs 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), + 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr), 'Spsr': cntrlRegNC('MISCREG_SPSR'), 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 'Fpsid': cntrlRegNC('MISCREG_FPSID'), diff -r 02508707978d -r 642c46ec6201 src/arch/arm/miscregs.hh --- a/src/arch/arm/miscregs.hh Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/miscregs.hh Wed May 04 20:41:48 2011 -0500 @@ -67,6 +67,7 @@ enum MiscRegIndex { MISCREG_CPSR = 0, + MISCREG_CPSR_Q, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ, @@ -209,7 +210,7 @@ unsigned crm, unsigned opc2); const char * const miscRegName[NUM_MISCREGS] = { - "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", + "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_mon", "spsr_und", "spsr_abt", "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", "mvfr0", "mvfr1", @@ -269,9 +270,9 @@ // This mask selects bits of the CPSR that actually go in the CondCodes // integer register to allow renaming. - static const uint32_t CondCodesMask = 0xF80F0000; + static const uint32_t CondCodesMask = 0xF00F0000; static const uint32_t CondCodesMaskF = 0xF0000000; - static const uint32_t CondCodesMaskQ = 0x08000000; + static const uint32_t CpsrMaskQ = 0x08000000; static const uint32_t CondCodesMaskGE = 0x000F0000; BitUnion32(SCTLR) diff -r 02508707978d -r 642c46ec6201 src/arch/arm/nativetrace.cc --- a/src/arch/arm/nativetrace.cc Wed May 04 20:39:54 2011 -0500 +++ b/src/arch/arm/nativetrace.cc Wed May 04 20:41:48 2011 -0500 @@ -117,7 +117,6 @@ //CPSR newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) | tc->readIntReg(INTREG_CONDCODES_F) | - tc->readIntReg(INTREG_CONDCODES_Q) | tc->readIntReg(INTREG_CONDCODES_GE); changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);