diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/faults.cc --- a/src/arch/arm/faults.cc Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/faults.cc Wed May 04 20:43:56 2011 -0500 @@ -107,7 +107,9 @@ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | - tc->readIntReg(INTREG_CONDCODES_F) | + tc->readIntReg(INTREG_CONDCODES_NZ) << CondCodesShiftNZ | + tc->readIntReg(INTREG_CONDCODES_C) << CondCodesShiftC | + tc->readIntReg(INTREG_CONDCODES_V) << CondCodesShiftV | tc->readIntReg(INTREG_CONDCODES_GE); Addr curPc M5_VAR_USED = tc->pcState().pc(); ITSTATE it = tc->pcState().itstate(); diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/intregs.hh --- a/src/arch/arm/intregs.hh Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/intregs.hh Wed May 04 20:43:56 2011 -0500 @@ -112,7 +112,9 @@ INTREG_UREG0, INTREG_UREG1, INTREG_UREG2, - INTREG_CONDCODES_F, + INTREG_CONDCODES_NZ, + INTREG_CONDCODES_C, + INTREG_CONDCODES_V, INTREG_CONDCODES_GE, INTREG_FPCONDCODES, diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/formats/fp.isa --- a/src/arch/arm/isa/formats/fp.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/formats/fp.isa Wed May 04 20:43:56 2011 -0500 @@ -2068,14 +2068,8 @@ return new Unknown(machInst); } if (rt == 0xf) { - CPSR cpsrMask = 0; - cpsrMask.n = 1; - cpsrMask.z = 1; - cpsrMask.c = 1; - cpsrMask.v = 1; if (specReg == MISCREG_FPSCR) { - return new VmrsApsrFpscr(machInst, INTREG_CONDCODES_F, - (IntRegIndex)specReg, (uint32_t)cpsrMask); + return new VmrsApsrFpscr(machInst); } else { return new Unknown(machInst); } diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/formats/pred.isa --- a/src/arch/arm/isa/formats/pred.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/formats/pred.isa Wed May 04 20:43:56 2011 -0500 @@ -53,7 +53,9 @@ _iv = %(ivValue)s & 1; _ic = %(icValue)s & 1; - CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28; + CondCodesNZ = _in << 1 | _iz; + CondCodesC = _ic; + CondCodesV = _iv; DPRINTF(Arm, "in = %%d\\n", _in); DPRINTF(Arm, "iz = %%d\\n", _iz); @@ -70,11 +72,11 @@ canOverflow = 'false' if flagtype == "none": - icReg = icImm = 'CondCodesF<29:>' - iv = 'CondCodesF<28:>' + icReg = icImm = 'CondCodesC' + iv = 'CondCodesV' elif flagtype == "llbit": - icReg = icImm = 'CondCodesF<29:>' - iv = 'CondCodesF<28:>' + icReg = icImm = 'CondCodesC' + iv = 'CondCodesV' negBit = 63 elif flagtype == "overflow": canOverflow = "true" @@ -89,9 +91,9 @@ icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)' iv = 'findOverflow(32, resTemp, op2, ~Rn)' else: - icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesF<29:>)' - icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesF<29:>)' - iv = 'CondCodesF<28:>' + icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)' + icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)' + iv = 'CondCodesV' return (calcCcCode % {"icValue" : icReg, "ivValue" : iv, "negBit" : negBit, @@ -106,11 +108,11 @@ negBit = 31 canOverflow = 'false' if flagtype == "none": - icValue = 'CondCodesF<29:>' - ivValue = 'CondCodesF<28:>' + icValue = 'CondCodesC' + ivValue = 'CondCodesV' elif flagtype == "llbit": - icValue = 'CondCodesF<29:>' - ivValue = 'CondCodesF<28:>' + icValue = 'CondCodesC' + ivValue = 'CondCodesV' negBit = 63 elif flagtype == "overflow": icVaule = ivValue = '0' @@ -126,20 +128,20 @@ ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)' elif flagtype == "modImm": icValue = 'rotated_carry' - ivValue = 'CondCodesF<28:>' + ivValue = 'CondCodesV' else: - icValue = '(rotate ? rotated_carry:CondCodesF<29:>)' - ivValue = 'CondCodesF<28:>' + icValue = '(rotate ? rotated_carry:CondCodesC)' + ivValue = 'CondCodesV' return calcCcCode % vars() }}; def format DataOp(code, flagtype = logic) {{ (regCcCode, immCcCode) = getCcCode(flagtype) regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>, - shift, CondCodesF<29:>); + shift, CondCodesC); op2 = op2;''' + code immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, - shift, CondCodesF<29:>); + shift, CondCodesC); op2 = op2;''' + code regIop = InstObjParams(name, Name, 'PredIntOp', {"code": regCode, diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/insts/data.isa --- a/src/arch/arm/isa/insts/data.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/insts/data.isa Wed May 04 20:43:56 2011 -0500 @@ -58,15 +58,17 @@ _iv = %(ivValue)s & 1; _ic = %(icValue)s & 1; - CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28; + CondCodesNZ = _in << 1 | _iz; + CondCodesC = _ic; + CondCodesV = _iv; DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", _in, _iz, _ic, _iv); ''' # Dict of code to set the carry flag. (imm, reg, reg-reg) - oldC = 'CondCodesF<29:>' - oldV = 'CondCodesF<28:>' + oldC = 'CondCodesC' + oldV = 'CondCodesV' carryCode = { "none": (oldC, oldC, oldC), "llbit": (oldC, oldC, oldC), @@ -101,8 +103,8 @@ secondOpRe = re.compile("secondOp") immOp2 = "imm" - regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)" - regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)" + regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)" def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ buildCc = True, buildNonCc = True, instFlags = []): @@ -238,11 +240,16 @@ if subsPcLr: code += ''' SCTLR sctlr = Sctlr; + uint32_t old_cpsr = Cpsr | CondCodesNZ << CondCodesShiftNZ | + CondCodesC << CondCodesShiftC | + CondCodesV << CondCodesShiftV | + CondCodesGE; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, - Spsr, 0xF, true, sctlr.nmfi); + cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - CondCodesF = CondCodesMaskF & newCpsr; + CondCodesNZ = (CondCodesMaskNZ & newCpsr) >> CondCodesShiftNZ; + CondCodesC = (CondCodesMaskC & newCpsr) >> CondCodesShiftC; + CondCodesV = (CondCodesMaskV & newCpsr) >> CondCodesShiftV; CondCodesGE = CondCodesMaskGE & newCpsr; NextThumb = ((CPSR)newCpsr).t; NextJazelle = ((CPSR)newCpsr).j; diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/insts/fp.isa --- a/src/arch/arm/isa/insts/fp.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/insts/fp.isa Wed May 04 20:43:56 2011 -0500 @@ -235,16 +235,17 @@ decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); - vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' - Dest = FpCondCodes & FpCondCodesMask; + vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + ''' + CondCodesNZ = (FpCondCodes & CondCodesMaskNZ) >> CondCodesShiftNZ; + CondCodesC = (FpCondCodes & CondCodesMaskC) >> CondCodesShiftC; + CondCodesV = (FpCondCodes & CondCodesMaskV) >> CondCodesShiftV; ''' - vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", + vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", { "code": vmrsApsrFpscrCode, "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeBefore"]) - header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); - decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); + "op_class": "SimdFloatMiscOp" }) + header_output += BasicDeclare.subst(vmrsApsrFpscrIop); + decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); vmovImmSCode = vfpEnabledCheckCode + ''' diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/insts/ldr.isa --- a/src/arch/arm/isa/insts/ldr.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/insts/ldr.isa Wed May 04 20:43:56 2011 -0500 @@ -106,7 +106,10 @@ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - URc = cpsr | CondCodesF | CondCodesGE; + URc = cpsr | CondCodesNZ << CondCodesShiftNZ | + CondCodesC << CondCodesShiftC | + CondCodesV << CondCodesShiftV | + CondCodesGE; URa = cSwap(Mem.ud, cpsr.e); URb = cSwap(Mem.ud >> 32, cpsr.e); ''' @@ -137,7 +140,7 @@ def __init__(self, *args, **kargs): super(LoadRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodesF<29:>)" + " shiftType, CondCodesC)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/insts/macromem.isa --- a/src/arch/arm/isa/insts/macromem.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/insts/macromem.isa Wed May 04 20:43:56 2011 -0500 @@ -89,11 +89,17 @@ microRetUopCode = ''' CPSR cpsr = Cpsr; SCTLR sctlr = Sctlr; + uint32_t old_cpsr = Cpsr | CondCodesNZ << CondCodesShiftNZ | + CondCodesC << CondCodesShiftC | + CondCodesV << CondCodesShiftV | + CondCodesGE; + uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE, - Spsr, 0xF, true, sctlr.nmfi); + cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - CondCodesF = CondCodesMaskF & newCpsr; + CondCodesNZ = (CondCodesMaskNZ & newCpsr) >> CondCodesShiftNZ; + CondCodesC = (CondCodesMaskC & newCpsr) >> CondCodesShiftC; + CondCodesV = (CondCodesMaskV & newCpsr) >> CondCodesShiftV; CondCodesGE = CondCodesMaskGE & newCpsr; IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) @@ -587,7 +593,7 @@ {'code': '''URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, - CondCodesF<29:>); + CondCodesC); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -603,7 +609,7 @@ {'code': '''URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, - CondCodesF<29:>); + CondCodesC); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -633,7 +639,9 @@ NextJazelle = ((CPSR)newCpsr).j; NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); - CondCodesF = CondCodesMaskF & newCpsr; + CondCodesNZ = (CondCodesMaskNZ & newCpsr) >> CondCodesShiftNZ; + CondCodesC = (CondCodesMaskC & newCpsr) >> CondCodesShiftC; + CondCodesV = (CondCodesMaskV & newCpsr) >> CondCodesShiftV; CondCodesGE = CondCodesMaskGE & newCpsr; ''' diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/insts/mem.isa --- a/src/arch/arm/isa/insts/mem.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/insts/mem.isa Wed May 04 20:43:56 2011 -0500 @@ -119,10 +119,35 @@ return (header_output, decoder_output, exec_output) def pickPredicate(blobs): + opt_nz = True + opt_c = True + opt_v = True for val in blobs.values(): - if re.search('(?> CondCodesShiftNZ; + CondCodesC = (CondCodesMaskC & newCpsr) >> CondCodesShiftC; + CondCodesV = (CondCodesMaskV & newCpsr) >> CondCodesShiftV; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", @@ -109,11 +119,16 @@ msrCpsrImmCode = ''' SCTLR sctlr = Sctlr; - uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm, - byteMask, false, sctlr.nmfi); + uint32_t old_cpsr = Cpsr | CondCodesNZ << CondCodesShiftNZ | + CondCodesC << CondCodesShiftC | + CondCodesV << CondCodesShiftV | + CondCodesGE; + uint32_t newCpsr = + cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - CondCodesF = CondCodesMaskF & newCpsr; + CondCodesNZ = (CondCodesMaskNZ & newCpsr) >> CondCodesShiftNZ; + CondCodesC = (CondCodesMaskC & newCpsr) >> CondCodesShiftC; + CondCodesV = (CondCodesMaskV & newCpsr) >> CondCodesShiftV; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", @@ -422,7 +437,7 @@ ''' selIop = InstObjParams("sel", "Sel", "RegRegRegOp", { "code": selCode, - "predicate_test": condPredicateTest }, []) + "predicate_test": predicateTest }, []) header_output += RegRegRegOpDeclare.subst(selIop) decoder_output += RegRegRegOpConstructor.subst(selIop) exec_output += PredOpExecute.subst(selIop) diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/insts/mult.isa --- a/src/arch/arm/isa/insts/mult.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/insts/mult.isa Wed May 04 20:43:56 2011 -0500 @@ -52,7 +52,7 @@ _in = (resTemp >> %(negBit)d) & 1; _iz = ((%(zType)s)resTemp == 0); - CondCodesF = _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF); + CondCodesNZ = _in << 1 | _iz; DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz); ''' diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/insts/str.isa --- a/src/arch/arm/isa/insts/str.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/insts/str.isa Wed May 04 20:43:56 2011 -0500 @@ -152,7 +152,7 @@ def __init__(self, *args, **kargs): super(StoreRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodesF<29:>)" + " shiftType, CondCodesC)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, index, shiftAmt, shiftType); diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/operands.isa --- a/src/arch/arm/isa/operands.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/operands.isa Wed May 04 20:43:56 2011 -0500 @@ -156,11 +156,24 @@ 'R3': intRegNPC('3'), #Pseudo integer condition code registers - 'CondCodesF': intRegCC('INTREG_CONDCODES_F'), + 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'), + 'CondCodesC': intRegCC('INTREG_CONDCODES_C'), + 'CondCodesV': intRegCC('INTREG_CONDCODES_V'), 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), - 'OptCondCodesF': intRegCC( - '''(condCode == COND_AL || condCode == COND_UC) ? - INTREG_ZERO : INTREG_CONDCODES_F'''), + 'OptCondCodesNZ': intRegCC( + '''(condCode == COND_AL || condCode == COND_UC || + condCode == COND_CC || condCode == COND_CS || + condCode == COND_VS || condCode == COND_VC) ? + INTREG_ZERO : INTREG_CONDCODES_NZ'''), + 'OptCondCodesC': intRegCC( + '''(condCode == COND_HI || condCode == COND_LS || + condCode == COND_CS || condCode == COND_CC) ? + INTREG_CONDCODES_C : INTREG_ZERO'''), + 'OptCondCodesV': intRegCC( + '''(condCode == COND_VS || condCode == COND_VC || + condCode == COND_GE || condCode == COND_LT || + condCode == COND_GT || condCode == COND_LE) ? + INTREG_CONDCODES_V : INTREG_ZERO'''), 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), #Abstracted floating point reg operands diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/templates/pred.isa --- a/src/arch/arm/isa/templates/pred.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/templates/pred.isa Wed May 04 20:43:56 2011 -0500 @@ -46,8 +46,8 @@ // let {{ - predicateTest = 'testPredicate(OptCondCodesF, condCode)' - condPredicateTest = 'testPredicate(CondCodesF, condCode)' + predicateTest = 'testPredicate(OptCondCodesNZ,OptCondCodesC,OptCondCodesV, condCode)' + condPredicateTest = 'testPredicate(CondCodesNZ,CondCodesC,CondCodesV, condCode)' }}; def template DataImmDeclare {{ diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/isa/templates/vfp.isa --- a/src/arch/arm/isa/templates/vfp.isa Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/isa/templates/vfp.isa Wed May 04 20:43:56 2011 -0500 @@ -62,6 +62,10 @@ if (op1 != (int)MISCREG_FPSCR) return disabledFault(); ''' + vmrsApsrEnabledCheckCode = ''' + if (!vfpEnabled(Cpacr, Cpsr)) + return disabledFault(); + ''' }}; def template FpRegRegOpDeclare {{ diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/miscregs.hh --- a/src/arch/arm/miscregs.hh Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/miscregs.hh Wed May 04 20:43:56 2011 -0500 @@ -272,6 +272,12 @@ // integer register to allow renaming. static const uint32_t CondCodesMask = 0xF00F0000; static const uint32_t CondCodesMaskF = 0xF0000000; + static const uint32_t CondCodesMaskNZ = 0xC0000000; + static const uint32_t CondCodesMaskC = 0x20000000; + static const uint32_t CondCodesMaskV = 0x10000000; + static const uint32_t CondCodesShiftNZ = 30; + static const uint32_t CondCodesShiftC = 29; + static const uint32_t CondCodesShiftV = 28; static const uint32_t CpsrMaskQ = 0x08000000; static const uint32_t CondCodesMaskGE = 0x000F0000; diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/nativetrace.cc --- a/src/arch/arm/nativetrace.cc Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/nativetrace.cc Wed May 04 20:43:56 2011 -0500 @@ -116,7 +116,9 @@ //CPSR newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) | - tc->readIntReg(INTREG_CONDCODES_F) | + tc->readIntReg(INTREG_CONDCODES_NZ) | + tc->readIntReg(INTREG_CONDCODES_C) | + tc->readIntReg(INTREG_CONDCODES_V) | tc->readIntReg(INTREG_CONDCODES_GE); changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); diff -r 642c46ec6201 -r da6f21cc0d8e src/arch/arm/utility.hh --- a/src/arch/arm/utility.hh Wed May 04 20:41:48 2011 -0500 +++ b/src/arch/arm/utility.hh Wed May 04 20:43:56 2011 -0500 @@ -65,24 +65,27 @@ } inline bool -testPredicate(CPSR cpsr, ConditionCode code) +testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code) { + bool n = (nz & 0x2) == 0x2; + bool z = (nz & 0x1); + switch (code) { - case COND_EQ: return cpsr.z; - case COND_NE: return !cpsr.z; - case COND_CS: return cpsr.c; - case COND_CC: return !cpsr.c; - case COND_MI: return cpsr.n; - case COND_PL: return !cpsr.n; - case COND_VS: return cpsr.v; - case COND_VC: return !cpsr.v; - case COND_HI: return (cpsr.c && !cpsr.z); - case COND_LS: return !(cpsr.c && !cpsr.z); - case COND_GE: return !(cpsr.n ^ cpsr.v); - case COND_LT: return (cpsr.n ^ cpsr.v); - case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); - case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); + case COND_EQ: return z; + case COND_NE: return !z; + case COND_CS: return c; + case COND_CC: return !c; + case COND_MI: return n; + case COND_PL: return !n; + case COND_VS: return v; + case COND_VC: return !v; + case COND_HI: return (c && !z); + case COND_LS: return !(c && !z); + case COND_GE: return !(n ^ v); + case COND_LT: return (n ^ v); + case COND_GT: return !(n ^ v || z); + case COND_LE: return (n ^ v || z); case COND_AL: return true; case COND_UC: return true; default: