diff -r 898dc56ed599 -r 0fbeeadfa8cf src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh	Mon May 16 16:36:09 2011 -0500
+++ b/src/cpu/o3/iew.hh	Mon May 16 16:36:31 2011 -0500
@@ -228,7 +228,7 @@
     {
         if (++wbOutstanding == wbMax)
             ableToIssue = false;
-        DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
+        DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
         assert(wbOutstanding <= wbMax);
 #ifdef DEBUG
         wbList.insert(sn);
diff -r 898dc56ed599 -r 0fbeeadfa8cf src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh	Mon May 16 16:36:09 2011 -0500
+++ b/src/cpu/o3/iew_impl.hh	Mon May 16 16:36:31 2011 -0500
@@ -1221,7 +1221,9 @@
 
         // Check if the instruction is squashed; if so then skip it
         if (inst->isSquashed()) {
-            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
+            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
+                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
+                         inst->seqNum);
 
             // Consider this instruction executed so that commit can go
             // ahead and retire the instruction.
diff -r 898dc56ed599 -r 0fbeeadfa8cf src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh	Mon May 16 16:36:09 2011 -0500
+++ b/src/cpu/o3/lsq_unit.hh	Mon May 16 16:36:31 2011 -0500
@@ -804,7 +804,12 @@
 
         ++lsqCacheBlocked;
 
-        iewStage->decrWb(load_inst->seqNum);
+        // If the first part of a split access succeeds, then let the LSQ
+        // handle the decrWb when completeDataAccess is called upon return
+        // of the requested first part of data
+        if (!completedFirst)
+            iewStage->decrWb(load_inst->seqNum);
+
         // There's an older load that's already going to squash.
         if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
             return NoFault;