diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -15,12 +15,14 @@
 
   // STATES
   state_declaration(State, desc="Cache states") {
+    // Stable States
     I, AccessPermission:Invalid, desc="Not Present/Invalid";
+    M, AccessPermission:Read_Write, desc="Modified";
+
+    // Transient States
     II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT";
-    M, AccessPermission:Read_Write, desc="Modified";
     MI, AccessPermission:Busy, desc="Modified, issued PUT";
     MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack";
-
     IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH";
     IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC";
   }
@@ -28,19 +30,19 @@
   // EVENTS
   enumeration(Event, desc="Cache events") {
     // From processor
-
     Load,       desc="Load request from processor";
     Ifetch,     desc="Ifetch request from processor";
     Store,      desc="Store request from processor";
 
+    // From network (directory)
     Data,       desc="Data from network";
     Fwd_GETX,        desc="Forward from network";
-
     Inv,        desc="Invalidate request from dir";
-
-    Replacement,  desc="Replace a block";
     Writeback_Ack,   desc="Ack from the directory for a writeback";
     Writeback_Nack,   desc="Nack from the directory for a writeback";
+
+    // Internally generated
+    Replacement,  desc="Replace a block";
   }
 
   // STRUCTURE DEFINITIONS
@@ -205,7 +207,7 @@
 
   action(a_issueRequest, "a", desc="Issue a request") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
-    out_msg.Address := address;
+      out_msg.Address := address;
       out_msg.Type := CoherenceRequestType:GETX;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
@@ -387,6 +389,13 @@
     m_popMandatoryQueue;
   }
 
+  transition(IM, Data, M) {
+    u_writeDataToCache;
+    sx_store_hit;
+    w_deallocateTBE;
+    n_popResponseQueue;
+  }
+
   transition(I, {Load, Ifetch}, IS) {
     v_allocateTBE;
     i_allocateL1CacheBlock;
@@ -402,13 +411,6 @@
     n_popResponseQueue;
   }
 
-  transition(IM, Data, M) {
-    u_writeDataToCache;
-    sx_store_hit;
-    w_deallocateTBE;
-    n_popResponseQueue;
-  }
-
   transition(M, Fwd_GETX, I) {
     e_sendData;
     o_popForwardedRequestQueue;