diff -r 062e5a73861c -r 15f3eb4bf0c0 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc	Sat Jun 11 01:50:10 2011 -0400
+++ b/src/arch/alpha/tlb.cc	Sat Jun 11 01:52:41 2011 -0400
@@ -457,7 +457,7 @@
         return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
     }
 
-    if (PcPAL(tc->pcState().pc())) {
+    if (PcPAL(req->getPC())) {
         mode = (req->getFlags() & Request::ALTMODE) ?
             (mode_type)ALT_MODE_AM(
                 tc->readMiscRegNoEffect(IPR_ALT_MODE))
diff -r 062e5a73861c -r 15f3eb4bf0c0 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc	Sat Jun 11 01:50:10 2011 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc	Sat Jun 11 01:52:41 2011 -0400
@@ -426,9 +426,16 @@
     ThreadID tid = inst->readTid();
 
     setupMemRequest(inst, cache_req, acc_size, flags);
+
+    //@todo: HACK: the DTB expects the correct PC in the ThreadContext
+    //       but how if the memory accesses are speculative? Shouldn't
+    //       we send along the requestor's PC to the translate functions?
+    ThreadContext *tc = cpu->thread[tid]->getTC();
+    PCState old_pc = tc->pcState();
+    tc->pcState() = inst->pcState();
     inst->fault =
-        _tlb->translateAtomic(cache_req->memReq,
-                              cpu->thread[tid]->getTC(), tlb_mode);
+        _tlb->translateAtomic(cache_req->memReq, tc, tlb_mode);
+    tc->pcState() = old_pc;
 
     if (inst->fault != NoFault) {
         DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "