diff -r 9fb150de362e src/cpu/inorder/resources/bpred_unit.cc --- a/src/cpu/inorder/resources/bpred_unit.cc Sun Jun 12 23:52:21 2011 -0700 +++ b/src/cpu/inorder/resources/bpred_unit.cc Mon Jun 13 15:17:10 2011 +0800 @@ -374,7 +374,10 @@ BPUpdate((*hist_it).pc.instAddr(), actually_taken, pred_hist.front().bpHistory); - BTB.update((*hist_it).pc.instAddr(), corrTarget, asid); +#if ISA_HAS_DELAY_SLOT + if (actually_taken) +#endif + BTB.update((*hist_it).pc.instAddr(), corrTarget, asid); DPRINTF(InOrderBPred, "[tid:%i]: Removing history for [sn:%i] " "PC %s.\n", tid, (*hist_it).seqNum, (*hist_it).pc); diff -r 9fb150de362e src/cpu/inorder/resources/branch_predictor.cc --- a/src/cpu/inorder/resources/branch_predictor.cc Sun Jun 12 23:52:21 2011 -0700 +++ b/src/cpu/inorder/resources/branch_predictor.cc Mon Jun 13 15:17:10 2011 +0800 @@ -88,7 +88,7 @@ // By default set target to NNPC (e.g. PC + 8) // so that a not-taken branch will update // correctly - pred_PC.advance(); + //pred_PC.advance(); #endif if (inst->isControl()) { @@ -153,7 +153,8 @@ #if ISA_HAS_DELAY_SLOT // We need to squash the actual branch , NOT the delay slot // in the branch predictor - squash_seq_num = squash_seq_num - 1; + if (!inst->isCondDelaySlot()) + squash_seq_num = squash_seq_num - 1; #endif if (squash_stage >= ThePipeline::BackEndStartStage) { diff -r 9fb150de362e src/cpu/inorder/resources/fetch_seq_unit.cc --- a/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 12 23:52:21 2011 -0700 +++ b/src/cpu/inorder/resources/fetch_seq_unit.cc Mon Jun 13 15:17:10 2011 +0800 @@ -139,8 +139,8 @@ "inst. updating PC to %s\n", tid, inst->seqNum, inst->readPredTarg()); #if ISA_HAS_DELAY_SLOT - pc[tid] = inst->pcState(); - advancePC(pc[tid], inst->staticInst); + //pc[tid] = inst->pcState(); + //advancePC(pc[tid], inst->staticInst); #endif } else if (inst->predTaken()) { // Taken Control