diff -r f980df284118 src/arch/mips/isa/formats/branch.isa
--- a/src/arch/mips/isa/formats/branch.isa	Mon Jun 20 18:58:31 2011 -0400
+++ b/src/arch/mips/isa/formats/branch.isa	Tue Jun 21 10:37:29 2011 +0800
@@ -234,7 +234,7 @@
         if x == 'Link':
             code += 'R31 = NNPC;\n'
         elif x == 'Likely':
-            not_taken_code = 'NNPC = NPC; NPC = PC;'
+            not_taken_code = 'NPC = NNPC; NNPC += 4;'
             inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )
@@ -273,7 +273,7 @@
         if x == 'Link':
             code += 'R32 = NNPC;'
         elif x == 'Likely':
-            not_taken_code = 'NNPC = NPC, NPC = PC;'
+            not_taken_code = 'NPC = NNPC; NNPC += 4;'
             inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )
diff -r f980df284118 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc	Mon Jun 20 18:58:31 2011 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc	Tue Jun 21 10:37:29 2011 +0800
@@ -337,12 +337,10 @@
 
 #if ISA_HAS_DELAY_SLOT
     if (staticInst && isControl()) {
-        TheISA::PCState nextPC = pc;
-        TheISA::advancePC(nextPC, staticInst);
 
         // Check to see if we should squash after the
         // branch or after a branch delay slot.
-        if (pc.nextInstAddr() == pc.instAddr() + sizeof(MachInst))
+        if (predPC.instAddr() == pc.instAddr() + sizeof(MachInst))
             squashSeqNum = seqNum + 1;
         else
             squashSeqNum = seqNum;
@@ -436,6 +434,12 @@
     return this->cpu->readMiscReg(misc_reg, threadNumber);
 }
 
+MiscReg
+InOrderDynInst::readMiscRegNoEffect(int misc_reg)
+{
+    return this->cpu->readMiscRegNoEffect(misc_reg, threadNumber);
+}
+
 
 /** Reads a misc. register, including any side-effects the read
  * might have as defined by the architecture.
@@ -534,6 +538,12 @@
 }
 
 void
+InOrderDynInst::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+{
+    this->cpu->setMiscRegNoEffect(misc_reg, val, threadNumber);
+}
+
+void
 InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
                                   ThreadID tid)
 {
diff -r f980df284118 src/cpu/inorder/resources/branch_predictor.cc
--- a/src/cpu/inorder/resources/branch_predictor.cc	Mon Jun 20 18:58:31 2011 -0400
+++ b/src/cpu/inorder/resources/branch_predictor.cc	Tue Jun 21 10:37:29 2011 +0800
@@ -105,6 +105,9 @@
                     // value
                     bool predict_taken = branchPred.predict(inst, pred_PC, tid);
 
+                    // This condition handles MIPS branch likely instructions.
+                    if (inst->isCondDelaySlot()) pred_PC.advance();
+
                     if (predict_taken) {
                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
                                 "predicted true.\n", tid, seq_num);
diff -r f980df284118 src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc	Mon Jun 20 18:58:31 2011 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc	Tue Jun 21 10:37:29 2011 +0800
@@ -119,8 +119,6 @@
 
       case UpdateTargetPC:
         {
-            assert(!inst->isCondDelaySlot()  &&
-                   "Not Handling Conditional Delay Slot");
 
             if (inst->isControl()) {
                 if (inst->isReturn() && !inst->predTaken()) {
@@ -134,7 +132,9 @@
                         toPrevStages->stageBlock[stage_num][tid] = true;
                     pcValid[tid] = false;
                     pcBlockStage[tid] = stage_num;
-                } else if (inst->predTaken()) {
+
+                // The 2nd condition handles MIPS branch likely instructions.
+                } else if (inst->predTaken() || (inst->isCondDelaySlot() && !inst->predTaken())) {
                     // Taken Control
                     inst->setSquashInfo(stage_num);
                     setupSquash(inst, stage_num, tid);