diff -r 01aa8afff718 -r 6e9831cc9c98 src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/arch/arm/isa/templates/mem.isa	Wed Jun 29 03:56:41 2011 -0700
@@ -209,7 +209,7 @@
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+                fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
                 %(memacc_code)s;
             }
 
@@ -280,8 +280,8 @@
             }
 
             if (fault == NoFault) {
-                fault = xc->writeBytes(dataPtr, %(size)d, EA,
-                                       memAccessFlags, NULL);
+                fault = xc->writeMem(dataPtr, %(size)d, EA,
+                                     memAccessFlags, NULL);
             }
 
             if (fault == NoFault) {
@@ -413,8 +413,8 @@
             }
 
             if (fault == NoFault) {
-                fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
-                                       memAccessFlags, NULL);
+                fault = xc->writeMem(memUnion.bytes, %(size)d, EA,
+                                     memAccessFlags, NULL);
             }
         } else {
             xc->setPredicate(false);
@@ -467,7 +467,7 @@
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+                fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
             }
         } else {
             xc->setPredicate(false);
diff -r 01aa8afff718 -r 6e9831cc9c98 src/arch/generic/memhelpers.hh
--- a/src/arch/generic/memhelpers.hh	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/arch/generic/memhelpers.hh	Wed Jun 29 03:56:41 2011 -0700
@@ -45,7 +45,7 @@
 readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
         MemT &mem, unsigned flags)
 {
-    return xc->readBytes(addr, (uint8_t *)&mem, sizeof(MemT), flags);
+    return xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
 }
 
 /// Extract the data returned from a timing mode read.
@@ -84,7 +84,7 @@
         traceData->setData(mem);
     }
     mem = TheISA::htog(mem);
-    return xc->writeBytes((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
+    return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
 }
 
 /// Write to memory in atomic mode.
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/base_dyn_inst.hh	Wed Jun 29 03:56:41 2011 -0700
@@ -124,10 +124,10 @@
         cpu->demapPage(vaddr, asn);
     }
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /** Splits a request in two if it crosses a dcache block. */
     void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@@ -841,8 +841,8 @@
 
 template<class Impl>
 Fault
-BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
-                             unsigned size, unsigned flags)
+BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
+                           unsigned size, unsigned flags)
 {
     reqMade = true;
     Request *req = NULL;
@@ -893,8 +893,8 @@
 
 template<class Impl>
 Fault
-BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
-                              Addr addr, unsigned flags, uint64_t *res)
+BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
+                            Addr addr, unsigned flags, uint64_t *res)
 {
     if (traceData) {
         traceData->setAddr(addr);
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/exec_context.hh
--- a/src/cpu/exec_context.hh	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/exec_context.hh	Wed Jun 29 03:56:41 2011 -0700
@@ -106,10 +106,10 @@
     /** Returns a pointer to the ThreadContext. */
     ThreadContext *tcBase();
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
 #if FULL_SYSTEM
     /** Somewhat Alpha-specific function that handles returning from
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.hh	Wed Jun 29 03:56:41 2011 -0700
@@ -613,10 +613,10 @@
     //
     ////////////////////////////////////////////
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
      *  Access Only valid for memory operations.
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.cc	Wed Jun 29 03:56:41 2011 -0700
@@ -559,15 +559,15 @@
 }
 
 Fault
-InOrderDynInst::readBytes(Addr addr, uint8_t *data,
-                          unsigned size, unsigned flags)
+InOrderDynInst::readMem(Addr addr, uint8_t *data,
+                        unsigned size, unsigned flags)
 {
     return cpu->read(this, addr, data, size, flags);
 }
 
 Fault
-InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
-                           Addr addr, unsigned flags, uint64_t *res)
+InOrderDynInst::writeMem(uint8_t *data, unsigned size,
+                         Addr addr, unsigned flags, uint64_t *res)
 {
     return cpu->write(this, data, size, addr, flags, res);
 }
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/simple/atomic.hh
--- a/src/cpu/simple/atomic.hh	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/simple/atomic.hh	Wed Jun 29 03:56:41 2011 -0700
@@ -131,10 +131,10 @@
     virtual void activateContext(int thread_num, int delay);
     virtual void suspendContext(int thread_num);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /**
      * Print state of address in memory system via PrintReq (for
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/simple/atomic.cc	Wed Jun 29 03:56:41 2011 -0700
@@ -299,8 +299,8 @@
 
 
 Fault
-AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
-                           unsigned size, unsigned flags)
+AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
+                         unsigned size, unsigned flags)
 {
     // use the CPU's statically allocated read request and packet objects
     Request *req = &data_read_req;
@@ -387,8 +387,8 @@
 
 
 Fault
-AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
-                            Addr addr, unsigned flags, uint64_t *res)
+AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
+                          Addr addr, unsigned flags, uint64_t *res)
 {
     // use the CPU's statically allocated write request and packet objects
     Request *req = &data_write_req;
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/simple/timing.hh	Wed Jun 29 03:56:41 2011 -0700
@@ -256,10 +256,10 @@
     virtual void activateContext(int thread_num, int delay);
     virtual void suspendContext(int thread_num);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     void fetch();
     void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
diff -r 01aa8afff718 -r 6e9831cc9c98 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Wed Jun 29 03:55:29 2011 -0700
+++ b/src/cpu/simple/timing.cc	Wed Jun 29 03:56:41 2011 -0700
@@ -432,8 +432,8 @@
 }
 
 Fault
-TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
-                           unsigned size, unsigned flags)
+TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
+                         unsigned size, unsigned flags)
 {
     Fault fault;
     const int asid = 0;
@@ -500,8 +500,8 @@
 }
 
 Fault
-TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
-                            Addr addr, unsigned flags, uint64_t *res)
+TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
+                          Addr addr, unsigned flags, uint64_t *res)
 {
     uint8_t *newData = new uint8_t[size];
     memcpy(newData, data, size);