diff -r f348cf78072c src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/isa.cc	Tue Jan 17 02:35:58 2012 +0800
@@ -478,11 +478,19 @@
             "Select:%u (%s) to %#x, with effect.\n",
             tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
 
-    MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
-
-    miscRegFile[misc_reg][reg_sel] = cp0_val;
-
-    scheduleCP0Update(tc->getCpuPtr(), 1);
+    switch (misc_reg)
+    {
+        case MISCREG_LLFLAG:
+        case MISCREG_LLADDR:
+            miscRegFile[misc_reg][reg_sel] = val;
+            break;
+        default:
+        {
+            MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
+            miscRegFile[misc_reg][reg_sel] = cp0_val;
+            scheduleCP0Update(tc->getCpuPtr(), 1);
+        }
+    }
 }
 
 /**