diff -r 471fd67f583a -r 4c516c8c1b0d src/cpu/base_dyn_inst.hh --- a/src/cpu/base_dyn_inst.hh Sun Jul 03 15:46:00 2011 -0700 +++ b/src/cpu/base_dyn_inst.hh Sun Jul 03 17:09:06 2011 -0700 @@ -133,6 +133,22 @@ void splitRequest(RequestPtr req, RequestPtr &sreqLow, RequestPtr &sreqHigh); + struct TranslationStub { + typedef RefCountingPtr >BaseDynInstPtr; + BaseDynInstPtr inst; + + TranslationStub(BaseDynInst *newInst) : inst(newInst) + {} + + void + finishTranslation(WholeTranslationState *state) + { + inst->finishTranslation(state); + inst = NULL; + delete this; + } + }; + /** Initiate a DTB address translation. */ void initiateTranslation(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, uint64_t *res, @@ -954,14 +970,15 @@ BaseTLB::Mode mode) { translationStarted = true; + typedef DataTranslation DataTranslation; if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { WholeTranslationState *state = new WholeTranslationState(req, NULL, res, mode); // One translation if the request isn't split. - DataTranslation > *trans = - new DataTranslation >(this, state); + DataTranslation *trans = new DataTranslation( + new TranslationStub(this), state); cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); if (!translationCompleted) { // Save memory requests. @@ -974,10 +991,10 @@ new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); // Two translations when the request is split. - DataTranslation > *stransLow = - new DataTranslation >(this, state, 0); - DataTranslation > *stransHigh = - new DataTranslation >(this, state, 1); + DataTranslation *stransLow = new DataTranslation( + new TranslationStub(this), state, 0); + DataTranslation *stransHigh = new DataTranslation( + new TranslationStub(this), state, 1); cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);