diff -r 8aa7fef3a28f -r 129282d020fe src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Mon Jul 11 04:48:24 2011 -0700
+++ b/src/cpu/o3/commit_impl.hh	Mon Jul 11 04:53:23 2011 -0700
@@ -713,9 +713,9 @@
         return;
     }
 
-    // Wait until the ROB is empty and all stores have drained in
-    // order to enter the interrupt.
-    if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
+    // Wait until all in flight instructions are finished before enterring
+    // the interrupt.
+    if (cpu->instList.empty()) {
         // Squash or record that I need to squash this cycle if
         // an interrupt needed to be handled.
         DPRINTF(Commit, "Interrupt detected.\n");