diff -r 64db4fd022ed -r 5e0e91095576 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py	Tue Jul 26 10:55:00 2011 -0500
+++ b/src/cpu/o3/O3CPU.py	Tue Jul 26 10:56:20 2011 -0500
@@ -121,6 +121,8 @@
     LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
     LSQCheckLoads = Param.Bool(True,
         "Should dependency violations be checked for loads & stores or just stores")
+    cycle_period = Param.Unsigned(250000,
+            "Number of load/store insts before the dep predictor should be invalidated")
     LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
     SSITSize = Param.Unsigned(1024, "Store set ID table size")
 
diff -r 64db4fd022ed -r 5e0e91095576 src/cpu/o3/mem_dep_unit_impl.hh
--- a/src/cpu/o3/mem_dep_unit_impl.hh	Tue Jul 26 10:55:00 2011 -0500
+++ b/src/cpu/o3/mem_dep_unit_impl.hh	Tue Jul 26 10:56:20 2011 -0500
@@ -45,8 +45,9 @@
 template <class MemDepPred, class Impl>
 MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
     : _name(params->name + ".memdepunit"),
-      depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
-      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
+      depPred(params->cycle_period, params->SSITSize, params->LFSTSize),
+      loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
+      storeBarrierSN(0), iqPtr(NULL)
 {
     DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
 }
@@ -85,7 +86,7 @@
     _name = csprintf("%s.memDep%d", params->name, tid);
     id = tid;
 
-    depPred.init(params->SSITSize, params->LFSTSize);
+    depPred.init(params->cycle_period, params->SSITSize, params->LFSTSize);
 }
 
 template <class MemDepPred, class Impl>
diff -r 64db4fd022ed -r 5e0e91095576 src/cpu/o3/store_set.hh
--- a/src/cpu/o3/store_set.hh	Tue Jul 26 10:55:00 2011 -0500
+++ b/src/cpu/o3/store_set.hh	Tue Jul 26 10:56:20 2011 -0500
@@ -63,18 +63,24 @@
     StoreSet() { };
 
     /** Creates store set predictor with given table sizes. */
-    StoreSet(int SSIT_size, int LFST_size);
+    StoreSet(uint64_t cycle_period, int SSIT_size, int LFST_size);
 
     /** Default destructor. */
     ~StoreSet();
 
     /** Initializes the store set predictor with the given table sizes. */
-    void init(int SSIT_size, int LFST_size);
+    void init(uint64_t cycle_period, int SSIT_size, int LFST_size);
 
     /** Records a memory ordering violation between the younger load
      * and the older store. */
     void violation(Addr store_PC, Addr load_PC);
 
+    /** Clears the store set predictor every so often so that all the
+     * entries aren't used and stores are constantly predicted as
+     * conflicting.
+     */
+    void checkClear();
+
     /** Inserts a load into the store set predictor.  This does nothing but
      * is included in case other predictors require a similar function.
      */
@@ -130,6 +136,11 @@
 
     typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
 
+    /** Number of loads/stores to process before wiping predictor so all
+     * entries don't get saturated
+     */
+    uint64_t cyclePeriod;
+
     /** Store Set ID Table size, in entries. */
     int SSITSize;
 
@@ -141,6 +152,9 @@
 
     // HACK: Hardcoded for now.
     int offsetBits;
+
+    /** Number of memory operations predicted since last clear of predictor */
+    int memOpsPred;
 };
 
 #endif // __CPU_O3_STORE_SET_HH__
diff -r 64db4fd022ed -r 5e0e91095576 src/cpu/o3/store_set.cc
--- a/src/cpu/o3/store_set.cc	Tue Jul 26 10:55:00 2011 -0500
+++ b/src/cpu/o3/store_set.cc	Tue Jul 26 10:56:20 2011 -0500
@@ -34,8 +34,8 @@
 #include "cpu/o3/store_set.hh"
 #include "debug/StoreSet.hh"
 
-StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
-    : SSITSize(_SSIT_size), LFSTSize(_LFST_size)
+StoreSet::StoreSet(uint64_t cycle_period, int _SSIT_size, int _LFST_size)
+    : cyclePeriod(cycle_period), SSITSize(_SSIT_size), LFSTSize(_LFST_size)
 {
     DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
     DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
@@ -68,6 +68,8 @@
     indexMask = SSITSize - 1;
 
     offsetBits = 2;
+
+    memOpsPred = 0;
 }
 
 StoreSet::~StoreSet()
@@ -75,10 +77,11 @@
 }
 
 void
-StoreSet::init(int _SSIT_size, int _LFST_size)
+StoreSet::init(uint64_t cycle_period, int _SSIT_size, int _LFST_size)
 {
     SSITSize = _SSIT_size;
     LFSTSize = _LFST_size;
+    cyclePeriod = cycle_period;
 
     DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
     DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
@@ -103,6 +106,8 @@
     indexMask = SSITSize - 1;
 
     offsetBits = 2;
+
+    memOpsPred = 0;
 }
 
 
@@ -180,8 +185,21 @@
 }
 
 void
+StoreSet::checkClear()
+{
+    memOpsPred++;
+    if (memOpsPred > cyclePeriod) {
+        DPRINTF(StoreSet, "Wiping predictor state beacuse %d ld/st executed\n",
+                cyclePeriod);
+        memOpsPred = 0;
+        clear();
+    }
+}
+
+void
 StoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
 {
+    checkClear();
     // Does nothing.
     return;
 }
@@ -193,6 +211,7 @@
 
     int store_SSID;
 
+    checkClear();
     assert(index < SSITSize);
 
     if (!validSSIT[index]) {