diff -r 7a9a7f2a3d46 -r 7ae5dc314c93 configs/example/fs.py --- a/configs/example/fs.py Wed Aug 03 18:25:30 2011 -0500 +++ b/configs/example/fs.py Sat Aug 06 02:39:59 2011 -0500 @@ -1,3 +1,4 @@ +# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. # Copyright (c) 2010 ARM Limited # All rights reserved. # @@ -37,6 +38,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi +# Authors: Brad Beckmann import optparse import os @@ -51,6 +53,9 @@ fatal("This script requires full-system mode (*_FS).") addToPath('../common') +addToPath('../ruby') + +import Ruby from FSConfig import * from SysPaths import * @@ -66,6 +71,10 @@ parser = optparse.OptionParser() # Simulation options +if buildEnv['PROTOCOL'] != 'None': + parser.add_option("--ruby", action="store_true") + if '--ruby' in sys.argv: + Ruby.define_options(parser) parser.add_option("--timesync", action="store_true", help="Prevent simulated time from getting ahead of real time") @@ -77,6 +86,7 @@ help="Provide the raw system without the linux specific bits") parser.add_option("--machine-type", action="store", type="choice", choices=ArmMachineType.map.keys(), default="RealView_PBX") + # Benchmark options parser.add_option("--dual", action="store_true", help="Simulate two systems attached with an ethernet link") @@ -98,17 +108,6 @@ print "Error: script doesn't take any positional arguments" sys.exit(1) -# driver system CPU is always simple... note this is an assignment of -# a class, not an instance. -DriveCPUClass = AtomicSimpleCPU -drive_mem_mode = 'atomic' - -# system under test can be any CPU -(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) - -TestCPUClass.clock = '2GHz' -DriveCPUClass.clock = '2GHz' - if options.benchmark: try: bm = Benchmarks[options.benchmark] @@ -122,85 +121,139 @@ else: bm = [SysConfig()] -np = options.num_cpus +if options.ruby: -if buildEnv['TARGET_ISA'] == "alpha": - test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) -elif buildEnv['TARGET_ISA'] == "mips": - test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) -elif buildEnv['TARGET_ISA'] == "sparc": - test_sys = makeSparcSystem(test_mem_mode, bm[0]) -elif buildEnv['TARGET_ISA'] == "x86": - test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) - setWorkCountOptions(test_sys, options) -elif buildEnv['TARGET_ISA'] == "arm": - test_sys = makeArmSystem(test_mem_mode, - options.machine_type, bm[0], - bare_metal=options.bare_metal) - setWorkCountOptions(test_sys, options) + # currently ruby fs only works in simple timing mode because ruby does not + # support atomic accesses by devices. Also ruby_fs currently assumes + # that is running a checkpoints that were created by ALPHA_FS under atomic + # mode. Since switch cpus are not defined in these checkpoints, we don't + # fast forward with the atomic cpu and instead set the FutureClass to None. + # Therefore the cpus resolve to the correct names and unserialize correctly. + + class CPUClass(TimingSimpleCPU): pass + test_mem_mode = 'timing' + FutureClass = None + + CPUClass.clock = options.clock + + if buildEnv['TARGET_ISA'] == "alpha": + test_sys = makeLinuxAlphaRubySystem(test_mem_mode, bm[0]) + elif buildEnv['TARGET_ISA'] == "x86": + test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True) + setWorkCountOptions(system, options) + else: + fatal("incapable of building non-alpha or non-x86 full system!") + + Ruby.create_system(options, test_sys, test_sys.piobus, test_sys._dma_devices) + + test_sys.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] + + for (i, cpu) in enumerate(test_sys.cpu): + # + # Tie the cpu ports to the correct ruby system ports + # + cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].port + cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].port + if buildEnv['TARGET_ISA'] == "x86": + cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].port + cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].port + cpu.interrupts.pio = test_sys.piobus.port + cpu.interrupts.int_port = test_sys.piobus.port + + if options.kernel is not None: + test_sys.kernel = binary(options.kernel) + root = Root(system = test_sys) + else: - fatal("incapable of building non-alpha or non-sparc full system!") + # system under test can be any CPU + (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) + TestCPUClass.clock = '2GHz' + np = options.num_cpus -if options.kernel is not None: - test_sys.kernel = binary(options.kernel) + if buildEnv['TARGET_ISA'] == "alpha": + test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) + elif buildEnv['TARGET_ISA'] == "mips": + test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) + elif buildEnv['TARGET_ISA'] == "sparc": + test_sys = makeSparcSystem(test_mem_mode, bm[0]) + elif buildEnv['TARGET_ISA'] == "x86": + test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) + setWorkCountOptions(test_sys, options) + elif buildEnv['TARGET_ISA'] == "arm": + test_sys = makeArmSystem(test_mem_mode, + options.machine_type, bm[0], + bare_metal=options.bare_metal) + setWorkCountOptions(test_sys, options) + else: + fatal("incapable of building non-alpha or non-sparc full system!") -if options.script is not None: - test_sys.readfile = options.script + if options.kernel is not None: + test_sys.kernel = binary(options.kernel) -test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] + if options.script is not None: + test_sys.readfile = options.script -CacheConfig.config_cache(options, test_sys) + test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] -if options.caches or options.l2cache: - if bm[0]: - mem_size = bm[0].mem() + CacheConfig.config_cache(options, test_sys) + + if options.caches or options.l2cache: + if bm[0]: + mem_size = bm[0].mem() + else: + mem_size = SysConfig().mem() + # For x86, we need to poke a hole for interrupt messages to get back to the + # CPU. These use a portion of the physical address space which has a + # non-zero prefix in the top nibble. Normal memory accesses have a 0 + # prefix. + if buildEnv['TARGET_ISA'] == 'x86': + test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)] + else: + test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] + test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)] + test_sys.iocache = IOCache(addr_range=mem_size) + test_sys.iocache.cpu_side = test_sys.iobus.port + test_sys.iocache.mem_side = test_sys.membus.port + + for i in xrange(np): + if options.fastmem: + test_sys.cpu[i].physmem_port = test_sys.physmem.port + + if buildEnv['TARGET_ISA'] == 'mips': + setMipsOptions(TestCPUClass) + + if len(bm) == 2: + + # driver system CPU is always simple... note this is an assignment of + # a class, not an instance. + DriveCPUClass = AtomicSimpleCPU + drive_mem_mode = 'atomic' + DriveCPUClass.clock = '2GHz' + + if buildEnv['TARGET_ISA'] == 'alpha': + drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) + elif buildEnv['TARGET_ISA'] == 'mips': + drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) + elif buildEnv['TARGET_ISA'] == 'sparc': + drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) + elif buildEnv['TARGET_ISA'] == 'x86': + drive_sys = makeX86System(drive_mem_mode, np, bm[1]) + elif buildEnv['TARGET_ISA'] == 'arm': + drive_sys = makeArmSystem(drive_mem_mode, + machine_options.machine_type, bm[1]) + drive_sys.cpu = DriveCPUClass(cpu_id=0) + drive_sys.cpu.connectAllPorts(drive_sys.membus) + if options.fastmem: + drive_sys.cpu.physmem_port = drive_sys.physmem.port + if options.kernel is not None: + drive_sys.kernel = binary(options.kernel) + + root = makeDualRoot(test_sys, drive_sys, options.etherdump) + elif len(bm) == 1: + root = Root(system=test_sys) else: - mem_size = SysConfig().mem() - # For x86, we need to poke a hole for interrupt messages to get back to the - # CPU. These use a portion of the physical address space which has a - # non-zero prefix in the top nibble. Normal memory accesses have a 0 - # prefix. - if buildEnv['TARGET_ISA'] == 'x86': - test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)] - else: - test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] - test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)] - test_sys.iocache = IOCache(addr_range=mem_size) - test_sys.iocache.cpu_side = test_sys.iobus.port - test_sys.iocache.mem_side = test_sys.membus.port - -for i in xrange(np): - if options.fastmem: - test_sys.cpu[i].physmem_port = test_sys.physmem.port - -if buildEnv['TARGET_ISA'] == 'mips': - setMipsOptions(TestCPUClass) - -if len(bm) == 2: - if buildEnv['TARGET_ISA'] == 'alpha': - drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) - elif buildEnv['TARGET_ISA'] == 'mips': - drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) - elif buildEnv['TARGET_ISA'] == 'sparc': - drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) - elif buildEnv['TARGET_ISA'] == 'x86': - drive_sys = makeX86System(drive_mem_mode, np, bm[1]) - elif buildEnv['TARGET_ISA'] == 'arm': - drive_sys = makeArmSystem(drive_mem_mode, - machine_options.machine_type, bm[1]) - drive_sys.cpu = DriveCPUClass(cpu_id=0) - drive_sys.cpu.connectAllPorts(drive_sys.membus) - if options.fastmem: - drive_sys.cpu.physmem_port = drive_sys.physmem.port - if options.kernel is not None: - drive_sys.kernel = binary(options.kernel) - - root = makeDualRoot(test_sys, drive_sys, options.etherdump) -elif len(bm) == 1: - root = Root(system=test_sys) -else: - print "Error I don't know how to create more than 2 systems." - sys.exit(1) + print "Error I don't know how to create more than 2 systems." + sys.exit(1) if options.timesync: root.time_sync_enable = True diff -r 7a9a7f2a3d46 -r 7ae5dc314c93 configs/example/ruby_fs.py --- a/configs/example/ruby_fs.py Wed Aug 03 18:25:30 2011 -0500 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,138 +0,0 @@ -# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Brad Beckmann - -# -# Full system configuraiton for ruby -# - -import os -import optparse -import sys -from os.path import join as joinpath - -import m5 -from m5.defines import buildEnv -from m5.objects import * -from m5.util import addToPath, panic - -if not buildEnv['FULL_SYSTEM']: - panic("This script requires full-system mode (*_FS).") - -addToPath('../common') -addToPath('../ruby') - -import Ruby - -from FSConfig import * -from SysPaths import * -from Benchmarks import * -import Simulation -from Caches import * - -# Get paths we might need. It's expected this file is in m5/configs/example. -config_path = os.path.dirname(os.path.abspath(__file__)) -config_root = os.path.dirname(config_path) -m5_root = os.path.dirname(config_root) - -parser = optparse.OptionParser() - -# Benchmark options -parser.add_option("-b", "--benchmark", action="store", type="string", - dest="benchmark", - help="Specify the benchmark to run. Available benchmarks: %s"\ - % DefinedBenchmarks) -parser.add_option("-o", "--options", default="", - help='The options to pass to the binary, use " " around the entire string') -parser.add_option("-i", "--input", default="", help="Read stdin from a file.") -parser.add_option("--output", default="", help="Redirect stdout to a file.") -parser.add_option("--errout", default="", help="Redirect stderr to a file.") - -# -# Add the ruby specific and protocol specific options -# -Ruby.define_options(parser) - -execfile(os.path.join(config_root, "common", "Options.py")) - -(options, args) = parser.parse_args() - -if args: - print "Error: script doesn't take any positional arguments" - sys.exit(1) - -if options.benchmark: - try: - bm = Benchmarks[options.benchmark] - except KeyError: - print "Error benchmark %s has not been defined." % options.benchmark - print "Valid benchmarks are: %s" % DefinedBenchmarks - sys.exit(1) -else: - bm = [SysConfig()] - -# -# currently ruby fs only works in simple timing mode because ruby does not -# support atomic accesses by devices. Also ruby_fs currently assumes -# that is running a checkpoints that were created by ALPHA_FS under atomic -# mode. Since switch cpus are not defined in these checkpoints, we don't -# fast forward with the atomic cpu and instead set the FutureClass to None. -# Therefore the cpus resolve to the correct names and unserialize correctly. -# -class CPUClass(TimingSimpleCPU): pass -test_mem_mode = 'timing' -FutureClass = None - -CPUClass.clock = options.clock - -if buildEnv['TARGET_ISA'] == "alpha": - system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0]) -elif buildEnv['TARGET_ISA'] == "x86": - system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True) - setWorkCountOptions(system, options) -else: - fatal("incapable of building non-alpha or non-x86 full system!") - -Ruby.create_system(options, system, system.piobus, system._dma_devices) - -system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] - -for (i, cpu) in enumerate(system.cpu): - # - # Tie the cpu ports to the correct ruby system ports - # - cpu.icache_port = system.ruby._cpu_ruby_ports[i].port - cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port - if buildEnv['TARGET_ISA'] == "x86": - cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port - cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port - cpu.interrupts.pio = system.piobus.port - cpu.interrupts.int_port = system.piobus.port - -root = Root(system = system) - -Simulation.run(options, root, system, FutureClass)