diff -r da07241bf10f -r 17fec22f7214 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh	Fri Sep 09 16:51:21 2011 -0500
+++ b/src/arch/arm/miscregs.hh	Fri Sep 09 16:51:22 2011 -0500
@@ -436,6 +436,11 @@
        Bitfield<31,30> or7;
    EndBitUnion(NMRR)
 
+   BitUnion32(CONTEXTIDR)
+      Bitfield<7,0>  asid;
+      Bitfield<31,8> procid;
+   EndBitUnion(CONTEXTIDR)
+
    BitUnion32(L2CTLR)
       Bitfield<2,0>   sataRAMLatency;
       Bitfield<4,3>   reserved_4_3;
diff -r da07241bf10f -r 17fec22f7214 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh	Fri Sep 09 16:51:21 2011 -0500
+++ b/src/arch/arm/tlb.hh	Fri Sep 09 16:51:22 2011 -0500
@@ -222,7 +222,7 @@
 protected:
     SCTLR sctlr;
     bool isPriv;
-    uint32_t contextId;
+    CONTEXTIDR contextId;
     PRRR prrr;
     NMRR nmrr;
     uint32_t dacr;
diff -r da07241bf10f -r 17fec22f7214 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc	Fri Sep 09 16:51:21 2011 -0500
+++ b/src/arch/arm/tlb.cc	Fri Sep 09 16:51:22 2011 -0500
@@ -467,6 +467,8 @@
     bool is_write = (mode == Write);
     bool is_priv = isPriv && !(flags & UserMode);
 
+    req->setAsid(contextId.asid);
+
     DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
             isPriv, flags & UserMode);
     // If this is a clrex instruction, provide a PA of 0 with no fault
diff -r da07241bf10f -r 17fec22f7214 src/mem/request.hh
--- a/src/mem/request.hh	Fri Sep 09 16:51:21 2011 -0500
+++ b/src/mem/request.hh	Fri Sep 09 16:51:22 2011 -0500
@@ -377,6 +377,13 @@
         return _asid;
     }
 
+    /** Accessor function for asid.*/
+    void
+    setAsid(int asid)
+    {
+        _asid = asid;
+    }
+
     /** Accessor function for asi.*/
     uint8_t
     getAsi()