diff -r 5b3eadfbe988 -r 75c3b7877fde src/arch/mips/faults.hh --- a/src/arch/mips/faults.hh Mon Sep 12 05:32:16 2011 -0700 +++ b/src/arch/mips/faults.hh Mon Sep 12 05:33:15 2011 -0700 @@ -93,8 +93,12 @@ class AddressErrorFault : public MipsFault { + protected: + Addr vaddr; + bool store; public: - AddressErrorFault(Addr vaddr) { badVAddr = vaddr; } + AddressErrorFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store) + {} #if FULL_SYSTEM void invoke(ThreadContext * tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); @@ -102,16 +106,6 @@ }; -class StoreAddressErrorFault : public MipsFault -{ - public: - StoreAddressErrorFault(Addr vaddr) { badVAddr = vaddr; } -#if FULL_SYSTEM - void invoke(ThreadContext * tc, - StaticInstPtr inst = StaticInst::nullStaticInstPtr); -#endif -}; - static inline Fault genMachineCheckFault() { return new MachineCheckFault; diff -r 5b3eadfbe988 -r 75c3b7877fde src/arch/mips/faults.cc --- a/src/arch/mips/faults.cc Mon Sep 12 05:32:16 2011 -0700 +++ b/src/arch/mips/faults.cc Mon Sep 12 05:33:15 2011 -0700 @@ -61,9 +61,6 @@ template <> FaultVals MipsFault::vals = { "Address Error", 0x0180 }; -template <> FaultVals MipsFault::vals = - { "Store Address Error", 0x0180 }; - template <> FaultVals MipsFault::vals = { "Syscall", 0x0180 }; @@ -177,20 +174,6 @@ } void -StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) -{ - DPRINTF(MipsPRA, "%s encountered.\n", name()); - setExceptionState(tc, 0x5); - tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); - - // Set new PC - Addr HandlerBase; - // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); - setHandlerPC(HandlerBase, tc); -} - -void TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst) { DPRINTF(MipsPRA, "%s encountered.\n", name()); @@ -244,8 +227,8 @@ AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) { DPRINTF(MipsPRA, "%s encountered.\n", name()); - setExceptionState(tc, 0x4); - tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); + setExceptionState(tc, store ? 0x5 : 0x4); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); // Set new PC Addr HandlerBase; diff -r 5b3eadfbe988 -r 75c3b7877fde src/arch/mips/tlb.cc --- a/src/arch/mips/tlb.cc Mon Sep 12 05:32:16 2011 -0700 +++ b/src/arch/mips/tlb.cc Mon Sep 12 05:33:15 2011 -0700 @@ -311,7 +311,7 @@ req->setPaddr(KSeg02Phys(vaddr)); if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || misaligned) { - return new AddressErrorFault(vaddr); + return new AddressErrorFault(vaddr, false); } } else if(IsKSeg1(vaddr)) { // Address will not be translated through TLB, set response, and go! @@ -331,7 +331,7 @@ uint8_t Asid = req->getAsid(); if (misaligned) { // Unaligned address! - return new AddressErrorFault(vaddr); + return new AddressErrorFault(vaddr, false); } PTE *pte = lookup(VPN,Asid); if (pte != NULL) { @@ -385,10 +385,7 @@ if (req->getVaddr() & (req->getSize() - 1)) { DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), req->getSize()); - if (write) - return new StoreAddressErrorFault(req->getVaddr()); - else - return new AddressErrorFault(req->getVaddr()); + return new AddressErrorFault(req->getVaddr(), write); } @@ -409,7 +406,7 @@ req->setPaddr(KSeg02Phys(vaddr)); if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || misaligned) { - return new StoreAddressErrorFault(vaddr); + return new AddressErrorFault(vaddr, true); } } else if(IsKSeg1(vaddr)) { // Address will not be translated through TLB, set response, and go! @@ -427,7 +424,7 @@ uint8_t Asid = req->getAsid(); PTE *pte = lookup(VPN, Asid); if (misaligned) { - return new StoreAddressErrorFault(vaddr); + return new AddressErrorFault(vaddr, true); } if (pte != NULL) { // Ok, found something