diff -r f4375ae04291 -r 4993cd1e8386 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh	Mon Sep 12 05:34:50 2011 -0700
+++ b/src/arch/mips/faults.hh	Mon Sep 12 05:35:31 2011 -0700
@@ -199,10 +199,13 @@
 #endif
 };
 
-class ItbRefillFault : public MipsFault<ItbRefillFault>
+class TlbRefillFault : public MipsFault<TlbRefillFault>
 {
+  protected:
+    bool store;
   public:
-    ItbRefillFault(Addr asid, Addr vaddr, Addr vpn)
+    TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool _store) :
+        store(_store)
     {
         entryHiAsid = asid;
         entryHiVPN2 = vpn >> 2;
@@ -216,27 +219,13 @@
 #endif
 };
 
-class DtbRefillFault : public MipsFault<DtbRefillFault>
+class TlbInvalidFault : public MipsFault<TlbInvalidFault>
 {
+  protected:
+    bool store;
   public:
-    DtbRefillFault(Addr asid, Addr vaddr, Addr vpn)
-    {
-        entryHiAsid = asid;
-        entryHiVPN2 = vpn >> 2;
-        entryHiVPN2X = vpn & 0x3;
-        badVAddr = vaddr;
-        contextBadVPN2 = vpn >> 2;
-    }
-#if FULL_SYSTEM
-    void invoke(ThreadContext * tc,
-            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
-};
-
-class ItbInvalidFault : public MipsFault<ItbInvalidFault>
-{
-  public:
-    ItbInvalidFault(Addr asid, Addr vaddr, Addr vpn)
+    TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool _store) :
+        store(_store)
     {
         entryHiAsid = asid;
         entryHiVPN2 = vpn >> 2;
@@ -267,23 +256,6 @@
 #endif
 };
 
-class DtbInvalidFault : public MipsFault<DtbInvalidFault>
-{
-  public:
-    DtbInvalidFault(Addr asid, Addr vaddr, Addr vpn)
-    {
-        entryHiAsid = asid;
-        entryHiVPN2 = vpn >> 2;
-        entryHiVPN2X = vpn & 0x3;
-        badVAddr = vaddr;
-        contextBadVPN2 = vpn >> 2;
-    }
-#if FULL_SYSTEM
-    void invoke(ThreadContext * tc,
-            StaticInst::StaticInstPtr inst = nullStaticInstPtr);
-#endif
-};
-
 class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
 {
   public:
diff -r f4375ae04291 -r 4993cd1e8386 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc	Mon Sep 12 05:34:50 2011 -0700
+++ b/src/arch/mips/faults.cc	Mon Sep 12 05:35:31 2011 -0700
@@ -85,17 +85,11 @@
 template <> FaultVals MipsFault<BreakpointFault>::vals =
     { "Breakpoint", 0x0180 };
 
-template <> FaultVals MipsFault<ItbInvalidFault>::vals =
-    { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 };
+template <> FaultVals MipsFault<TlbInvalidFault>::vals =
+    { "Invalid TLB Entry Exception", 0x0180 };
 
-template <> FaultVals MipsFault<ItbRefillFault>::vals =
-    { "TLB Refill Exception (I-Fetch/LW)", 0x0180 };
-
-template <> FaultVals MipsFault<DtbInvalidFault>::vals =
-    { "Invalid TLB Entry Exception (Store)", 0x0180 };
-
-template <> FaultVals MipsFault<DtbRefillFault>::vals =
-    { "TLB Refill Exception (Store)", 0x0180 };
+template <> FaultVals MipsFault<TlbRefillFault>::vals =
+    { "TLB Refill Exception", 0x0180 };
 
 template <> FaultVals MipsFault<TLBModifiedFault>::vals =
     { "TLB Modified Exception", 0x0180 };
@@ -199,9 +193,10 @@
 }
 
 void
-DtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
+    setExceptionState(tc, store ? 0x3 : 0x2);
 
     tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
     EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
@@ -213,8 +208,6 @@
     ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
     context.badVPN2 = contextBadVPN2;
     tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
-    setExceptionState(tc, 0x3);
-
 
     // Set new PC
     Addr HandlerBase;
@@ -238,35 +231,11 @@
 }
 
 void
-ItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
-    DPRINTF(MipsPRA, "%s encountered.\n", name());
-    setExceptionState(tc, 0x2);
-    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
-    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
-    entryHi.asid = entryHiAsid;
-    entryHi.vpn2 = entryHiVPN2;
-    entryHi.vpn2x = entryHiVPN2X;
-    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
-
-    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
-    context.badVPN2 = contextBadVPN2;
-    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
-
-
-    // Set new PC
-    Addr HandlerBase;
-    // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
-    setHandlerPC(HandlerBase,tc);
-    DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
-            HandlerBase, tc->readMiscReg(MISCREG_EPC));
-}
-
-void
-ItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
+    setExceptionState(tc, store ? 0x3 : 0x2);
+
     Addr HandlerBase;
     tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
     EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
@@ -288,41 +257,6 @@
         // Offset 0x000
         HandlerBase = tc->readMiscReg(MISCREG_EBASE);
     }
-
-    setExceptionState(tc, 0x2);
-    setHandlerPC(HandlerBase, tc);
-}
-
-void
-DtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
-    // Set new PC
-    DPRINTF(MipsPRA, "%s encountered.\n", name());
-    Addr HandlerBase;
-    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
-    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
-    entryHi.asid = entryHiAsid;
-    entryHi.vpn2 = entryHiVPN2;
-    entryHi.vpn2x = entryHiVPN2X;
-    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
-
-    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
-    context.badVPN2 = contextBadVPN2;
-    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
-
-    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
-    // Since handler depends on EXL bit, must check EXL bit before setting it!!
-    // See MIPS ARM Vol 3, Revision 2, Page 38
-    if (status.exl) {
-        // Offset 0x180 - General Exception Vector
-        HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
-    } else {
-        // Offset 0x000
-        HandlerBase = tc->readMiscReg(MISCREG_EBASE);
-    }
-
-    setExceptionState(tc, 0x3);
-
     setHandlerPC(HandlerBase, tc);
 }
 
diff -r f4375ae04291 -r 4993cd1e8386 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc	Mon Sep 12 05:34:50 2011 -0700
+++ b/src/arch/mips/tlb.cc	Mon Sep 12 05:35:31 2011 -0700
@@ -350,7 +350,7 @@
           }
 
           if (Valid == false) {
-              return new ItbInvalidFault(Asid, vaddr, vpn);
+              return new InvalidFault(Asid, vaddr, vpn, false);
           } else {
               // Ok, this is really a match, set paddr
               Addr PAddr;
@@ -366,7 +366,7 @@
             }
         } else {
             // Didn't find any match, return a TLB Refill Exception
-            return new ItbRefillFault(Asid, vaddr, vpn);
+            return new RefillFault(Asid, vaddr, vpn, false);
         }
     }
     return checkCacheability(req);
@@ -445,7 +445,7 @@
             }
 
             if (Valid == false) {
-                return new DtbInvalidFault(Asid, vaddr, VPN);
+                return new InvalidFault(Asid, vaddr, VPN, true);
             } else {
                 // Ok, this is really a match, set paddr
                 if (!Dirty) {
@@ -464,7 +464,7 @@
             }
         } else {
             // Didn't find any match, return a TLB Refill Exception
-            return new DtbRefillFault(Asid, vaddr, VPN);
+            return new RefillFault(Asid, vaddr, VPN, true);
         }
     }
     return checkCacheability(req);