diff -r 525a82b11094 -r 562f236f6216 src/arch/alpha/faults.hh
--- a/src/arch/alpha/faults.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/arch/alpha/faults.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -84,11 +84,6 @@
     bool isAlignmentFault() const {return true;}
 };
 
-static inline Fault genMachineCheckFault()
-{
-    return new MachineCheckFault;
-}
-
 class ResetFault : public AlphaFault
 {
   private:
diff -r 525a82b11094 -r 562f236f6216 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/arch/alpha/tlb.cc	Sat Sep 24 18:08:51 2011 -0700
@@ -36,6 +36,7 @@
 #include "arch/alpha/faults.hh"
 #include "arch/alpha/pagetable.hh"
 #include "arch/alpha/tlb.hh"
+#include "arch/generic/debugfaults.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
@@ -434,8 +435,9 @@
     }
 
     // check that the physical address is ok (catch bad physical addresses)
-    if (req->getPaddr() & ~PAddrImplMask)
-        return genMachineCheckFault();
+    if (req->getPaddr() & ~PAddrImplMask) {
+        return new MachineCheckFault();
+    }
 
     return checkCacheability(req, true);
 
@@ -562,8 +564,9 @@
     }
 
     // check that the physical address is ok (catch bad physical addresses)
-    if (req->getPaddr() & ~PAddrImplMask)
-        return genMachineCheckFault();
+    if (req->getPaddr() & ~PAddrImplMask) {
+        return new MachineCheckFault();
+    }
 
     return checkCacheability(req);
 }
diff -r 525a82b11094 -r 562f236f6216 src/arch/arm/faults.hh
--- a/src/arch/arm/faults.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/arch/arm/faults.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -242,11 +242,6 @@
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
-static inline Fault genMachineCheckFault()
-{
-    return new Reset();
-}
-
 // A fault that flushes the pipe, excluding the faulting instructions
 class ArmSev : public ArmFaultVals<ArmSev>
 {
diff -r 525a82b11094 -r 562f236f6216 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/arch/mips/faults.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -128,11 +128,6 @@
     bool isMachineCheckFault() { return true; }
 };
 
-static inline Fault genMachineCheckFault()
-{
-    return new MachineCheckFault;
-}
-
 class ResetFault : public MipsFault<ResetFault>
 {
   public:
diff -r 525a82b11094 -r 562f236f6216 src/arch/power/faults.hh
--- a/src/arch/power/faults.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/arch/power/faults.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -85,13 +85,6 @@
     }
 };
 
-
-static inline Fault
-genMachineCheckFault()
-{
-    return new MachineCheckFault();
-}
-
 } // namespace PowerISA
 
 #endif // __ARCH_POWER_FAULTS_HH__
diff -r 525a82b11094 -r 562f236f6216 src/arch/sparc/faults.hh
--- a/src/arch/sparc/faults.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/arch/sparc/faults.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -287,13 +287,6 @@
 #endif
 };
 
-static inline Fault
-genMachineCheckFault()
-{
-    return new InternalProcessorError;
-}
-
-
 } // namespace SparcISA
 
 #endif // __SPARC_FAULTS_HH__
diff -r 525a82b11094 -r 562f236f6216 src/arch/x86/faults.hh
--- a/src/arch/x86/faults.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/arch/x86/faults.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -363,11 +363,6 @@
         {}
     };
 
-    static inline Fault genMachineCheckFault()
-    {
-        return new MachineCheck;
-    }
-
     class SIMDFloatingPointFault : public X86Fault
     {
       public:
diff -r 525a82b11094 -r 562f236f6216 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/cpu/o3/lsq_unit.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -38,6 +38,7 @@
 #include <queue>
 
 #include "arch/faults.hh"
+#include "arch/generic/debugfaults.hh"
 #include "arch/isa_traits.hh"
 #include "arch/locked_mem.hh"
 #include "arch/mmapped_ipr.hh"
@@ -568,7 +569,9 @@
             delete sreqLow;
             delete sreqHigh;
         }
-        return TheISA::genMachineCheckFault();
+        return new GenericISA::M5PanicFault(
+                "Uncachable load [sn:%llx] PC %s\n",
+                load_inst->seqNum, load_inst->pcState());
     }
 
     // Check the SQ for any previous stores that might lead to forwarding
diff -r 525a82b11094 -r 562f236f6216 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh	Sat Sep 24 17:12:23 2011 -0700
+++ b/src/cpu/o3/lsq_unit_impl.hh	Sat Sep 24 18:08:51 2011 -0700
@@ -41,6 +41,7 @@
  *          Korey Sewell
  */
 
+#include "arch/generic/debugfaults.hh"
 #include "arch/locked_mem.hh"
 #include "base/str.hh"
 #include "config/the_isa.hh"
@@ -533,13 +534,16 @@
                     if (!memDepViolator ||
                             ld_inst->seqNum < memDepViolator->seqNum) {
                         DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
-                                " and [sn:%lli] at address %#x\n", inst->seqNum,
-                                ld_inst->seqNum, ld_eff_addr1);
+                                "and [sn:%lli] at address %#x\n",
+                                inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
                         memDepViolator = ld_inst;
 
                         ++lsqMemOrderViolation;
 
-                        return TheISA::genMachineCheckFault();
+                        return new GenericISA::M5PanicFault(
+                                "Detected fault with inst [sn:%lli] and "
+                                "[sn:%lli] at address %#x\n",
+                                inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
                     }
                 }
 
@@ -556,14 +560,16 @@
                 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum)
                     break;
 
-                DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and [sn:%lli]"
-                        " at address %#x\n", inst->seqNum, ld_inst->seqNum,
-                        ld_eff_addr1);
+                DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
+                        "[sn:%lli] at address %#x\n",
+                        inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
                 memDepViolator = ld_inst;
 
                 ++lsqMemOrderViolation;
 
-                return TheISA::genMachineCheckFault();
+                return new GenericISA::M5PanicFault("Detected fault with "
+                        "inst [sn:%lli] and [sn:%lli] at address %#x\n",
+                        inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
             }
         }