diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py	Mon Oct 31 00:24:27 2011 -0500
@@ -67,18 +67,18 @@
 def macroop ADD_LOCKED_M_I
 {
     limm t2, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADD_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADD_M_R
@@ -98,17 +98,17 @@
 
 def macroop ADD_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADD_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADD_R_M
@@ -168,18 +168,18 @@
 def macroop SUB_LOCKED_M_I
 {
     limm t2, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop SUB_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop SUB_M_R
@@ -199,17 +199,17 @@
 
 def macroop SUB_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop SUB_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADC_R_R
@@ -243,18 +243,18 @@
 def macroop ADC_LOCKED_M_I
 {
     limm t2, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADC_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADC_M_R
@@ -274,17 +274,17 @@
 
 def macroop ADC_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADC_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop ADC_R_M
@@ -344,18 +344,18 @@
 def macroop SBB_LOCKED_M_I
 {
     limm t2, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop SBB_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop SBB_M_R
@@ -375,17 +375,17 @@
 
 def macroop SBB_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop SBB_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop NEG_R
@@ -410,16 +410,16 @@
 
 def macroop NEG_LOCKED_M
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop NEG_LOCKED_P
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 '''
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py	Mon Oct 31 00:24:27 2011 -0500
@@ -58,17 +58,17 @@
 
 def macroop INC_LOCKED_M
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop INC_LOCKED_P
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop DEC_R
@@ -93,16 +93,16 @@
 
 def macroop DEC_LOCKED_M
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop DEC_LOCKED_P
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 '''
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py	Mon Oct 31 00:24:27 2011 -0500
@@ -114,10 +114,10 @@
     limm t1, imm, dataSize=asz
     limm t4, 1
     roli t4, t4, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sexti t0, t1, imm, flags=(CF,)
     xor t1, t1, t4
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop BTC_LOCKED_P_I {
@@ -125,10 +125,10 @@
     limm t1, imm, dataSize=asz
     limm t4, 1
     roli t4, t4, imm
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sexti t0, t1, imm, flags=(CF,)
     xor t1, t1, t4
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop BTC_R_R {
@@ -168,10 +168,10 @@
     lea t3, flatseg, [dsz, t3, base], dataSize=asz
     limm t4, 1
     rol t4, t4, reg
-    ldstl t1, seg, [scale, index, t3], disp
+    ldstl t1, seg, [scale, index, t3], disp, nonSpec=True, memBar=True
     sext t0, t1, reg, flags=(CF,)
     xor t1, t1, t4
-    stul t1, seg, [scale, index, t3], disp
+    stul t1, seg, [scale, index, t3], disp, nonSpec=True, memBar=True
 };
 
 def macroop BTC_LOCKED_P_R {
@@ -180,10 +180,10 @@
     srai t3, t2, ldsz, dataSize=asz
     limm t4, 1
     rol t4, t4, reg
-    ldstl t1, seg, [dsz, t3, t7], disp
+    ldstl t1, seg, [dsz, t3, t7], disp, nonSpec=True, memBar=True
     sext t0, t1, reg, flags=(CF,)
     xor t1, t1, t4
-    stul t1, seg, [dsz, t3, t7], disp
+    stul t1, seg, [dsz, t3, t7], disp, nonSpec=True, memBar=True
 };
 
 def macroop BTR_R_I {
@@ -218,10 +218,10 @@
     limm t1, imm, dataSize=asz
     limm t4, "(uint64_t(-(2ULL)))"
     roli t4, t4, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sexti t0, t1, imm, flags=(CF,)
     and t1, t1, t4
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop BTR_LOCKED_P_I {
@@ -229,10 +229,10 @@
     limm t1, imm, dataSize=asz
     limm t4, "(uint64_t(-(2ULL)))"
     roli t4, t4, imm
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sexti t0, t1, imm, flags=(CF,)
     and t1, t1, t4
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop BTR_R_R {
@@ -272,10 +272,10 @@
     lea t3, flatseg, [dsz, t3, base], dataSize=asz
     limm t4, "(uint64_t(-(2ULL)))"
     rol t4, t4, reg
-    ldstl t1, seg, [scale, index, t3], disp
+    ldstl t1, seg, [scale, index, t3], disp, nonSpec=True, memBar=True
     sext t0, t1, reg, flags=(CF,)
     and t1, t1, t4
-    stul t1, seg, [scale, index, t3], disp
+    stul t1, seg, [scale, index, t3], disp, nonSpec=True, memBar=True
 };
 
 def macroop BTR_LOCKED_P_R {
@@ -284,10 +284,10 @@
     srai t3, t2, ldsz, dataSize=asz
     limm t4, "(uint64_t(-(2ULL)))"
     rol t4, t4, reg
-    ldstl t1, seg, [dsz, t3, t7], disp
+    ldstl t1, seg, [dsz, t3, t7], disp, nonSpec=True, memBar=True
     sext t0, t1, reg, flags=(CF,)
     and t1, t1, t4
-    stul t1, seg, [dsz, t3, t7], disp
+    stul t1, seg, [dsz, t3, t7], disp, nonSpec=True, memBar=True
 };
 
 def macroop BTS_R_I {
@@ -322,10 +322,10 @@
     limm t1, imm, dataSize=asz
     limm t4, 1
     roli t4, t4, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sexti t0, t1, imm, flags=(CF,)
     or t1, t1, t4
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop BTS_LOCKED_P_I {
@@ -333,10 +333,10 @@
     limm t1, imm, dataSize=asz
     limm t4, 1
     roli t4, t4, imm
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sexti t0, t1, imm, flags=(CF,)
     or t1, t1, t4
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop BTS_R_R {
@@ -377,10 +377,10 @@
     lea t3, flatseg, [dsz, t3, base], dataSize=asz
     limm t4, 1
     rol t4, t4, reg
-    ldstl t1, seg, [scale, index, t3], disp
+    ldstl t1, seg, [scale, index, t3], disp, nonSpec=True, memBar=True
     sext t0, t1, reg, flags=(CF,)
     or t1, t1, t4
-    stul t1, seg, [scale, index, t3], disp
+    stul t1, seg, [scale, index, t3], disp, nonSpec=True, memBar=True
 };
 
 def macroop BTS_LOCKED_P_R {
@@ -390,9 +390,9 @@
     lea t3, flatseg, [dsz, t3, base], dataSize=asz
     limm t4, 1
     rol t4, t4, reg
-    ldstl t1, seg, [1, t3, t7], disp
+    ldstl t1, seg, [1, t3, t7], disp, nonSpec=True, memBar=True
     sext t0, t1, reg, flags=(CF,)
     or t1, t1, t4
-    stul t1, seg, [1, t3, t7], disp
+    stul t1, seg, [1, t3, t7], disp, nonSpec=True, memBar=True
 };
 '''
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py	Mon Oct 31 00:24:27 2011 -0500
@@ -80,16 +80,16 @@
 
 def macroop XCHG_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
-    stul reg, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
+    stul reg, seg, sib, disp, nonSpec=True, memBar=True
     mov reg, reg, t1
 };
 
 def macroop XCHG_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
-    stul reg, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
+    stul reg, seg, riprel, disp, nonSpec=True, memBar=True
     mov reg, reg, t1
 };
 '''
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py	Mon Oct 31 00:24:27 2011 -0500
@@ -43,25 +43,25 @@
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=asz
         ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-            nonSpec=True
+            nonSpec=True, memBar=True
     };
 
     def macroop IN_R_R {
         zexti t2, regm, 15, dataSize=8
         ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-            nonSpec=True
+            nonSpec=True, memBar=True
     };
 
     def macroop OUT_I_R {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=8
         st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-            nonSpec=True
+            nonSpec=True, memBar=True
     };
 
     def macroop OUT_R_R {
         zexti t2, reg, 15, dataSize=8
         st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-            nonSpec=True
+            nonSpec=True, memBar=True
     };
 '''
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py	Mon Oct 31 00:24:27 2011 -0500
@@ -46,8 +46,8 @@
     zexti t2, reg, 15, dataSize=8
 
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-        nonSpec=True
-    st t6, es, [1, t0, rdi]
+        nonSpec=True, memBar=True
+    st t6, es, [1, t0, rdi], memBar=True
 
     add rdi, rdi, t3, dataSize=asz
 };
@@ -65,8 +65,8 @@
 
 topOfLoop:
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-        nonSpec=True
-    st t6, es, [1, t0, rdi]
+        nonSpec=True, memBar=True
+    st t6, es, [1, t0, rdi], memBar=True
 
     subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
     add rdi, rdi, t3, dataSize=asz
@@ -84,9 +84,9 @@
 
     zexti t2, reg, 15, dataSize=8
 
-    ld t6, ds, [1, t0, rsi]
+    ld t6, ds, [1, t0, rsi], memBar=True
     st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-        nonSpec=True
+        nonSpec=True, memBar=True
 
     add rsi, rsi, t3, dataSize=asz
 };
@@ -103,9 +103,9 @@
     zexti t2, reg, 15, dataSize=8
 
 topOfLoop:
-    ld t6, ds, [1, t0, rsi]
+    ld t6, ds, [1, t0, rsi], memBar=True
     st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
-        nonSpec=True
+        nonSpec=True, memBar=True
 
     subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
     add rsi, rsi, t3, dataSize=asz
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/logical.py
--- a/src/arch/x86/isa/insts/general_purpose/logical.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/logical.py	Mon Oct 31 00:24:27 2011 -0500
@@ -61,18 +61,18 @@
 def macroop OR_LOCKED_M_I
 {
     limm t2, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop OR_LOCKED_P_I
 {
     limm t2, imm
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop OR_M_R
@@ -92,17 +92,17 @@
 
 def macroop OR_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop OR_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop OR_R_M
@@ -155,18 +155,18 @@
 def macroop XOR_LOCKED_M_I
 {
     limm t2, imm
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop XOR_LOCKED_P_I
 {
     limm t2, imm
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop XOR_M_R
@@ -186,17 +186,17 @@
 
 def macroop XOR_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop XOR_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop XOR_R_M
@@ -255,19 +255,19 @@
 
 def macroop AND_LOCKED_M_I
 {
-    ldstl t2, seg, sib, disp
+    ldstl t2, seg, sib, disp, nonSpec=True, memBar=True
     limm t1, imm
     and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
-    stul t2, seg, sib, disp
+    stul t2, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop AND_LOCKED_P_I
 {
     rdip t7
-    ldstl t2, seg, riprel, disp
+    ldstl t2, seg, riprel, disp, nonSpec=True, memBar=True
     limm t1, imm
     and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
-    stul t2, seg, riprel, disp
+    stul t2, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop AND_M_R
@@ -287,17 +287,17 @@
 
 def macroop AND_LOCKED_M_R
 {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop AND_LOCKED_P_R
 {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
 };
 
 def macroop NOT_R
@@ -326,17 +326,17 @@
 def macroop NOT_LOCKED_M
 {
     limm t1, -1
-    ldstl t2, seg, sib, disp
+    ldstl t2, seg, sib, disp, nonSpec=True, memBar=True
     xor t2, t2, t1
-    stul t2, seg, sib, disp
+    stul t2, seg, sib, disp, nonSpec=True, memBar=True
 };
 
 def macroop NOT_LOCKED_P
 {
     limm t1, -1
     rdip t7
-    ldstl t2, seg, riprel, disp
+    ldstl t2, seg, riprel, disp, nonSpec=True, memBar=True
     xor t2, t2, t1
-    stul t2, seg, riprel, disp
+    stul t2, seg, riprel, disp, nonSpec=True, memBar=True
 };
 '''
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/insts/general_purpose/semaphores.py
--- a/src/arch/x86/isa/insts/general_purpose/semaphores.py	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py	Mon Oct 31 00:24:27 2011 -0500
@@ -62,21 +62,21 @@
 };
 
 def macroop CMPXCHG_LOCKED_M_R {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
 
     mov t1, t1, reg, flags=(CZF,)
-    stul t1, seg, sib, disp
+    stul t1, seg, sib, disp, nonSpec=True, memBar=True
     mov rax, rax, t1, flags=(nCZF,)
 };
 
 def macroop CMPXCHG_LOCKED_P_R {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
 
     mov t1, t1, reg, flags=(CZF,)
-    stul t1, seg, riprel, disp
+    stul t1, seg, riprel, disp, nonSpec=True, memBar=True
     mov rax, rax, t1, flags=(nCZF,)
 };
 
@@ -96,17 +96,17 @@
 };
 
 def macroop XADD_LOCKED_M_R {
-    ldstl t1, seg, sib, disp
+    ldstl t1, seg, sib, disp, nonSpec=True, memBar=True
     add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t2, seg, sib, disp
+    stul t2, seg, sib, disp, nonSpec=True, memBar=True
     mov reg, reg, t1
 };
 
 def macroop XADD_LOCKED_P_R {
     rdip t7
-    ldstl t1, seg, riprel, disp
+    ldstl t1, seg, riprel, disp, nonSpec=True, memBar=True
     add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    stul t2, seg, riprel, disp
+    stul t2, seg, riprel, disp, nonSpec=True, memBar=True
     mov reg, reg, t1
 };
 
@@ -122,8 +122,8 @@
 def macroop CMPXCHG8B_%(suffix)s {
     %(rdip)s
     lea t1, seg, %(sib)s, disp, dataSize=asz
-    ldst%(l)s t2, seg, [1, t0, t1], 0
-    ldst%(l)s t3, seg, [1, t0, t1], dsz
+    ldst%(l)s t2, seg, [1, t0, t1], 0 %(flag)s
+    ldst%(l)s t3, seg, [1, t0, t1], dsz %(flag)s
 
     sub t0, rax, t2, flags=(ZF,)
     br label("doneComparing"), flags=(nCZF,)
@@ -139,23 +139,25 @@
     mov rdx, rdx, t3, flags=(nCZF,)
 
     # Write to memory
-    st%(ul)s t3, seg, [1, t0, t1], dsz
-    st%(ul)s t2, seg, [1, t0, t1], 0
+    st%(ul)s t3, seg, [1, t0, t1], dsz %(flag)s
+    st%(ul)s t2, seg, [1, t0, t1], 0 %(flag)s
 };
 '''
 
 microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
                               "l": "", "ul": "",
-                              "suffix": "M"}
+                              "suffix": "M", "flag":""}
 microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
                               "l": "", "ul": "",
-                              "suffix": "P"}
+                              "suffix": "P", "flag":""}
 microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
                               "l": "l", "ul": "ul",
-                              "suffix": "LOCKED_M"}
+                              "suffix": "LOCKED_M",
+                              "flag":", nonSpec=True, memBar=True"}
 microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
                               "l": "l", "ul": "ul",
-                              "suffix": "LOCKED_P"}
+                              "suffix": "LOCKED_P",
+                              "flag":", nonSpec=True, memBar=True"}
 
 #let {{
 #    class XCHG(Inst):
diff -r ed4ab740741c -r 53ac67e04b96 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa	Sun Oct 30 20:14:48 2011 -0500
+++ b/src/arch/x86/isa/microops/ldstop.isa	Mon Oct 31 00:24:27 2011 -0500
@@ -272,8 +272,8 @@
 
 let {{
     class LdStOp(X86Microop):
-        def __init__(self, data, segment, addr, disp,
-                dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
+        def __init__(self, data, segment, addr, disp, dataSize, addressSize,
+                     baseFlags, atCPL0, prefetch, nonSpec, memBar):
             self.data = data
             [self.scale, self.index, self.base] = addr
             self.disp = disp
@@ -289,6 +289,8 @@
                 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
             if nonSpec:
                 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
+            if memBar:
+                self.instFlags += " | (1ULL << StaticInst::IsMemBarrier)"
             self.memFlags += " | (machInst.legacy.addr ? " + \
                              "(AddrSizeFlagBit << FlagShift) : 0)"
 
@@ -308,8 +310,8 @@
             return allocator
 
     class BigLdStOp(X86Microop):
-        def __init__(self, data, segment, addr, disp,
-                dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
+        def __init__(self, data, segment, addr, disp, dataSize, addressSize,
+                     baseFlags, atCPL0, prefetch, nonSpec, memBar):
             self.data = data
             [self.scale, self.index, self.base] = addr
             self.disp = disp
@@ -325,6 +327,8 @@
                 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
             if nonSpec:
                 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
+            if memBar:
+                self.instFlags += " | (1ULL << StaticInst::IsMemBarrier)"
             self.memFlags += " | (machInst.legacy.addr ? " + \
                              "(AddrSizeFlagBit << FlagShift) : 0)"
 
@@ -393,10 +397,10 @@
             def __init__(self, data, segment, addr, disp = 0,
                     dataSize="env.dataSize",
                     addressSize="env.addressSize",
-                    atCPL0=False, prefetch=False, nonSpec=False):
+                    atCPL0=False, prefetch=False, nonSpec=False, memBar=False):
                 super(LoadOp, self).__init__(data, segment, addr,
                         disp, dataSize, addressSize, mem_flags,
-                        atCPL0, prefetch, nonSpec)
+                        atCPL0, prefetch, nonSpec, memBar)
                 self.className = Name
                 self.mnemonic = name
 
@@ -435,10 +439,10 @@
             def __init__(self, data, segment, addr, disp = 0,
                     dataSize="env.dataSize",
                     addressSize="env.addressSize",
-                    atCPL0=False, nonSpec=False):
+                    atCPL0=False, nonSpec=False, memBar=False):
                 super(StoreOp, self).__init__(data, segment, addr, disp,
                         dataSize, addressSize, mem_flags, atCPL0, False,
-                        nonSpec)
+                        nonSpec, memBar)
                 self.className = Name
                 self.mnemonic = name
 
@@ -463,7 +467,7 @@
         def __init__(self, data, segment, addr, disp = 0,
                 dataSize="env.dataSize", addressSize="env.addressSize"):
             super(LeaOp, self).__init__(data, segment, addr, disp,
-                    dataSize, addressSize, "0", False, False, False)
+                    dataSize, addressSize, "0", False, False, False, False)
             self.className = "Lea"
             self.mnemonic = "lea"
 
@@ -483,7 +487,7 @@
                 addressSize="env.addressSize"):
             super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
                     addr, disp, dataSize, addressSize, "0", False, False,
-                    False)
+                    False, False)
             self.className = "Tia"
             self.mnemonic = "tia"
 
@@ -495,7 +499,7 @@
                 addressSize="env.addressSize", atCPL0=False):
             super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
                     addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
-                    atCPL0, False, False)
+                    atCPL0, False, False, False)
             self.className = "Cda"
             self.mnemonic = "cda"