diff -r ed4ab740741c -r c2b17b56d754 src/arch/x86/isa/insts/general_purpose/input_output/general_io.py --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Sun Oct 30 20:14:48 2011 -0500 +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Mon Oct 31 11:50:20 2011 -0500 @@ -43,25 +43,25 @@ .adjust_imm trimImm(8) limm t1, imm, dataSize=asz ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True }; def macroop IN_R_R { zexti t2, regm, 15, dataSize=8 ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True }; def macroop OUT_I_R { .adjust_imm trimImm(8) limm t1, imm, dataSize=8 st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True }; def macroop OUT_R_R { zexti t2, reg, 15, dataSize=8 st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True }; ''' diff -r ed4ab740741c -r c2b17b56d754 src/arch/x86/isa/insts/general_purpose/input_output/string_io.py --- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py Sun Oct 30 20:14:48 2011 -0500 +++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py Mon Oct 31 11:50:20 2011 -0500 @@ -46,7 +46,7 @@ zexti t2, reg, 15, dataSize=8 ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True st t6, es, [1, t0, rdi] add rdi, rdi, t3, dataSize=asz @@ -65,7 +65,7 @@ topOfLoop: ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True st t6, es, [1, t0, rdi] subi rcx, rcx, 1, flags=(EZF,), dataSize=asz @@ -86,7 +86,7 @@ ld t6, ds, [1, t0, rsi] st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True add rsi, rsi, t3, dataSize=asz }; @@ -105,7 +105,7 @@ topOfLoop: ld t6, ds, [1, t0, rsi] st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ - nonSpec=True + nonSpec=True, memBar=True subi rcx, rcx, 1, flags=(EZF,), dataSize=asz add rsi, rsi, t3, dataSize=asz diff -r ed4ab740741c -r c2b17b56d754 src/arch/x86/isa/microops/ldstop.isa --- a/src/arch/x86/isa/microops/ldstop.isa Sun Oct 30 20:14:48 2011 -0500 +++ b/src/arch/x86/isa/microops/ldstop.isa Mon Oct 31 11:50:20 2011 -0500 @@ -272,8 +272,8 @@ let {{ class LdStOp(X86Microop): - def __init__(self, data, segment, addr, disp, - dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): + def __init__(self, data, segment, addr, disp, dataSize, addressSize, + baseFlags, atCPL0, prefetch, nonSpec, memBar): self.data = data [self.scale, self.index, self.base] = addr self.disp = disp @@ -289,6 +289,8 @@ self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" if nonSpec: self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" + if memBar: + self.instFlags += " | (1ULL << StaticInst::IsMemBarrier)" self.memFlags += " | (machInst.legacy.addr ? " + \ "(AddrSizeFlagBit << FlagShift) : 0)" @@ -308,8 +310,8 @@ return allocator class BigLdStOp(X86Microop): - def __init__(self, data, segment, addr, disp, - dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): + def __init__(self, data, segment, addr, disp, dataSize, addressSize, + baseFlags, atCPL0, prefetch, nonSpec, memBar): self.data = data [self.scale, self.index, self.base] = addr self.disp = disp @@ -325,6 +327,8 @@ self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" if nonSpec: self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" + if memBar: + self.instFlags += " | (1ULL << StaticInst::IsMemBarrier)" self.memFlags += " | (machInst.legacy.addr ? " + \ "(AddrSizeFlagBit << FlagShift) : 0)" @@ -393,10 +397,10 @@ def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize", - atCPL0=False, prefetch=False, nonSpec=False): + atCPL0=False, prefetch=False, nonSpec=False, memBar=False): super(LoadOp, self).__init__(data, segment, addr, disp, dataSize, addressSize, mem_flags, - atCPL0, prefetch, nonSpec) + atCPL0, prefetch, nonSpec, memBar) self.className = Name self.mnemonic = name @@ -407,11 +411,36 @@ defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 'Data = Mem & mask(dataSize * 8);', '(StoreCheck << FlagShift)') - defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', - 'Data = Mem & mask(dataSize * 8);', - '(StoreCheck << FlagShift) | Request::LOCKED') defineMicroLoadOp('Ldfp', 'FpData_uqw = Mem;', big = False) + #Definition of Ldstl + iops = [InstObjParams("ldstl", "Ldstl", 'X86ISA::LdStOp', + {"code": 'Data = merge(Data, Mem, dataSize);', + "ea_code": calculateEA})] + iops += [InstObjParams("ldstl", "Ldstl" + "Big", 'X86ISA::LdStOp', + {"code": 'Data = Mem & mask(dataSize * 8);', + "ea_code": calculateEA})] + for iop in iops: + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLoadExecute.subst(iop) + exec_output += MicroLoadInitiateAcc.subst(iop) + exec_output += MicroLoadCompleteAcc.subst(iop) + + class LdstlOp(BigLdStOp): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", + addressSize="env.addressSize", + atCPL0=False, prefetch=False): + super(LdstlOp, self).__init__(data, segment, addr, disp, + dataSize, addressSize, + '(StoreCheck << FlagShift) | Request::LOCKED', + atCPL0, prefetch, True, True) + self.className = "Ldstl" + self.mnemonic = "ldstl" + + microopClasses["ldstl"] = LdstlOp + def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"): global header_output global decoder_output @@ -435,21 +464,42 @@ def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize", - atCPL0=False, nonSpec=False): + atCPL0=False, nonSpec=False, memBar=False): super(StoreOp, self).__init__(data, segment, addr, disp, dataSize, addressSize, mem_flags, atCPL0, False, - nonSpec) + nonSpec, memBar) self.className = Name self.mnemonic = name microopClasses[name] = StoreOp defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') - defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', - mem_flags="Request::LOCKED") defineMicroStoreOp('Stfp', 'Mem = FpData_uqw;') defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") + # Definition of Stul + iop = InstObjParams("stul", "Stul", 'X86ISA::LdStOp', + {"code": 'Mem = pick(Data, 2, dataSize);', + "complete_code": "", "ea_code": calculateEA}) + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroStoreExecute.subst(iop) + exec_output += MicroStoreInitiateAcc.subst(iop) + exec_output += MicroStoreCompleteAcc.subst(iop) + + class StulOp(LdStOp): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", + addressSize="env.addressSize", atCPL0=False): + super(StulOp, self).__init__(data, segment, addr, disp, + dataSize, addressSize, "Request::LOCKED", atCPL0, + False, True, True) + self.className = "Stul" + self.mnemonic = "stul" + + microopClasses["stul"] = StulOp + + # Definition of Lea iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', {"code": "Data = merge(Data, EA, dataSize);", "ea_code": ''' @@ -463,7 +513,7 @@ def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize"): super(LeaOp, self).__init__(data, segment, addr, disp, - dataSize, addressSize, "0", False, False, False) + dataSize, addressSize, "0", False, False, False, False) self.className = "Lea" self.mnemonic = "lea" @@ -483,7 +533,7 @@ addressSize="env.addressSize"): super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, addr, disp, dataSize, addressSize, "0", False, False, - False) + False, False) self.className = "Tia" self.mnemonic = "tia" @@ -495,7 +545,7 @@ addressSize="env.addressSize", atCPL0=False): super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, addr, disp, dataSize, addressSize, "Request::NO_ACCESS", - atCPL0, False, False) + atCPL0, False, False, False) self.className = "Cda" self.mnemonic = "cda"