diff -r 163253a6e979 -r 75f97a274c5c src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py	Thu Nov 03 15:24:29 2011 -0500
+++ b/src/cpu/BaseCPU.py	Thu Nov 03 15:24:38 2011 -0500
@@ -182,14 +182,14 @@
         self.dcache_port = dc.cpu_side
         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
         if buildEnv['FULL_SYSTEM']:
-            if buildEnv['TARGET_ISA'] == 'x86':
+            if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and iwc and dwc:
                 self.itb_walker_cache = iwc
                 self.dtb_walker_cache = dwc
                 self.itb.walker.port = iwc.cpu_side
                 self.dtb.walker.port = dwc.cpu_side
                 self._cached_ports += ["itb_walker_cache.mem_side", \
                                        "dtb_walker_cache.mem_side"]
-            elif buildEnv['TARGET_ISA'] == 'arm':
+            elif buildEnv['TARGET_ISA'] in ['x86', 'arm']:
                 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):