diff -r 87a6eaef78d0 -r 0e644df459ad configs/common/Caches.py
--- a/configs/common/Caches.py	Thu Nov 03 15:24:48 2011 -0500
+++ b/configs/common/Caches.py	Thu Nov 03 15:24:58 2011 -0500
@@ -33,7 +33,7 @@
     block_size = 64
     latency = '1ns'
     mshrs = 10
-    tgts_per_mshr = 5
+    tgts_per_mshr = 20
     is_top_level = True
 
 class L2Cache(BaseCache):
diff -r 87a6eaef78d0 -r 0e644df459ad src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py	Thu Nov 03 15:24:48 2011 -0500
+++ b/src/cpu/o3/O3CPU.py	Thu Nov 03 15:24:58 2011 -0500
@@ -148,5 +148,3 @@
 
     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
         BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
-        self.icache.tgts_per_mshr = 20
-        self.dcache.tgts_per_mshr = 20