diff -r 5bc1486bcf8d -r f8941b9c8629 src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/arch/alpha/isa_traits.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -129,6 +129,8 @@
 
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
+// Memory consistency model
+const bool HasTSO = false;
 
 } // namespace AlphaISA
 
diff -r 5bc1486bcf8d -r f8941b9c8629 src/arch/arm/isa_traits.hh
--- a/src/arch/arm/isa_traits.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/arch/arm/isa_traits.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -113,6 +113,8 @@
 
     // Memory accesses cannot be unaligned
     const bool HasUnalignedMemAcc = true;
+    // Memory consistency model
+    const bool HasTSO = false;
 
     enum InterruptTypes
     {
diff -r 5bc1486bcf8d -r f8941b9c8629 src/arch/mips/isa_traits.hh
--- a/src/arch/mips/isa_traits.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/arch/mips/isa_traits.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -161,6 +161,8 @@
 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 
 const bool HasUnalignedMemAcc = true;
+// Memory consistency model
+const bool HasTSO = false;
 
 } // namespace MipsISA
 
diff -r 5bc1486bcf8d -r f8941b9c8629 src/arch/power/isa_traits.hh
--- a/src/arch/power/isa_traits.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/arch/power/isa_traits.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -71,6 +71,8 @@
 
 // Memory accesses can be unaligned
 const bool HasUnalignedMemAcc = true;
+// Memory consistency model
+const bool HasTSO = false;
 
 } // namespace PowerISA
 
diff -r 5bc1486bcf8d -r f8941b9c8629 src/arch/sparc/isa_traits.hh
--- a/src/arch/sparc/isa_traits.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/arch/sparc/isa_traits.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -95,6 +95,8 @@
 
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
+// Memory consistency model
+const bool HasTSO = false;
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__
diff -r 5bc1486bcf8d -r f8941b9c8629 src/arch/x86/isa_traits.hh
--- a/src/arch/x86/isa_traits.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/arch/x86/isa_traits.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -73,6 +73,8 @@
 
     // Memory accesses can be unaligned
     const bool HasUnalignedMemAcc = true;
+    // Memory consistency model
+    const bool HasTSO = true;
 
     const ExtMachInst NoopMachInst = {
         0x0,                            // No legacy prefixes.
diff -r 5bc1486bcf8d -r f8941b9c8629 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/cpu/o3/lsq_unit.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -453,6 +453,9 @@
     /** Has the blocked load been handled. */
     bool loadBlockedHandled;
 
+    /** Whether or not a store is in flight. */
+    bool storeInFlight;
+
     /** The sequence number of the blocked load. */
     InstSeqNum blockedLoadSeqNum;
 
diff -r 5bc1486bcf8d -r f8941b9c8629 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh	Sat Jan 07 10:12:23 2012 -0600
+++ b/src/cpu/o3/lsq_unit_impl.hh	Sat Jan 07 10:12:25 2012 -0600
@@ -138,7 +138,7 @@
 LSQUnit<Impl>::LSQUnit()
     : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
       isStoreBlocked(false), isLoadBlocked(false),
-      loadBlockedHandled(false), hasPendingPkt(false)
+      loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false)
 {
 }
 
@@ -770,6 +770,7 @@
            storeWBIdx != storeTail &&
            storeQueue[storeWBIdx].inst &&
            storeQueue[storeWBIdx].canWB &&
+           ((!TheISA::HasTSO) || (!storeInFlight)) &&
            usedPorts < cachePorts) {
 
         if (isStoreBlocked || lsq->cacheBlocked()) {
@@ -1090,6 +1091,10 @@
 #endif
     }
 
+    if (TheISA::HasTSO) {
+        storeInFlight = true;
+    }
+
     incrStIdx(storeWBIdx);
 }
 
@@ -1163,6 +1168,10 @@
 
     storeQueue[store_idx].inst->setCompleted();
 
+    if (TheISA::HasTSO) {
+        storeInFlight = false;
+    }
+
     // Tell the checker we've completed this instruction.  Some stores
     // may get reported twice to the checker, but the checker can
     // handle that case.