diff -r e70d031cb5f9 -r cca29fccc4b1 src/mem/SConscript
--- a/src/mem/SConscript	Mon Nov 28 04:35:55 2011 -0500
+++ b/src/mem/SConscript	Mon Nov 28 18:15:15 2011 +0000
@@ -42,6 +42,13 @@
 Source('tport.cc')
 Source('mport.cc')
 
+Source('port_proxy.cc')
+
+if env['FULL_SYSTEM']:
+    Source('fs_translating_proxy.cc')
+else:
+    Source('se_translating_proxy.cc')
+
 if env['TARGET_ISA'] != 'no':
     SimObject('PhysicalMemory.py')
     Source('dram.cc')
diff -r e70d031cb5f9 -r cca29fccc4b1 src/mem/fs_translating_proxy.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/fs_translating_proxy.hh	Mon Nov 28 18:15:15 2011 +0000
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Geza Lore
+ */
+
+/**
+ * @file FSTranslatingProxy Object Declaration.
+ * Port proxies are used when non
+ * structural entities need access to the memory system. Proxy objects
+ * replace the previous FunctionalPort, TranslatingPort and VirtualPort
+ * objects, which provided the same functionality as the proxies, but
+ * were instances of ports not corresponding to real structural ports of
+ * the simulated system.
+ * @sa PortProxy
+ * @sa SETranslatingProxy
+ */
+
+#ifndef __MEM_FS_TRANSLATING_PROXY_HH__
+#define __MEM_FS_TRANSLATING_PROXY_HH__
+
+#include <string>
+
+#include "arch/vtophys.hh"
+#include "mem/port_proxy.hh"
+
+class ThreadContext;
+
+/**
+ * This object is a proxy for a structural port,
+ * to be used for debug accesses in FS mode.
+ *
+ * This proxy object is used when non structural entities
+ * (e.g. thread contexts, object file loaders) need access to the
+ * memory system. It calls the corresponding functions on the underlying
+ * structural port, and provides templatized convenience access functions.
+ *
+ * The addresses are interpreted as virtual addresses, address translation
+ * is performed using the standard translation mechanism of the actual ISA.
+ *
+ * @sa PortProxy
+ * @sa SETranslatingProxy
+ */
+class FSTranslatingProxy : public PortProxy
+{
+  private:
+    ThreadContext *_tc;
+
+  public:
+    FSTranslatingProxy(ThreadContext *tc);
+    FSTranslatingProxy(Port &port);
+    FSTranslatingProxy(Port *port);
+    virtual ~FSTranslatingProxy();
+
+  public:
+    /**
+     * Read size bytes memory at address and store in p.
+     * @sa MasterPort::readMem
+     */
+    virtual void readMem( Addr address, uint8_t* p, int size);
+
+    /**
+     * Write size bytes from p to address.
+     * @sa MasterPort::writeMem
+     */
+    virtual void writeMem(Addr address, uint8_t* p, int size);
+
+    /**
+     * Fill size bytes starting at addr with byte value val.
+     * @sa MasterPort::setMem
+     */
+    virtual void setMem(  Addr address, uint8_t  v, int size);
+
+    /**
+     * Read sizeof(T) bytes from address and return as object T.
+     */
+    template <typename T>
+    T read(Addr address);
+
+    /**
+     * Write object T to address. Writes sizeof(T) bytes.
+     */
+    template <typename T>
+    void write(Addr address, T data);
+
+    /**
+     * Read sizeof(T) bytes from address and return as object T.
+     * Performs Guest to Host endianness transform.
+     */
+    template <typename T>
+    T readGtoH(Addr address);
+
+    /**
+     * Write object T to address. Writes sizeof(T) bytes.
+     * Performs Host to Guest endianness transform.
+     */
+    template <typename T>
+    void writeHtoG(Addr address, T data);
+};
+
+template <typename T>
+T
+FSTranslatingProxy::read(Addr address)
+{
+    if (_tc == NULL) {
+        return PortProxy::read<T>(TheISA::vtophys(address));
+    } else {
+        return PortProxy::read<T>(TheISA::vtophys(_tc,address));
+    }
+}
+
+template <typename T>
+void
+FSTranslatingProxy::write(Addr address, T data)
+{
+    if (_tc == NULL) {
+        PortProxy::write<T>(TheISA::vtophys(address), data);
+    } else {
+        PortProxy::write<T>(TheISA::vtophys(_tc,address), data);
+    }
+}
+
+template <typename T>
+T
+FSTranslatingProxy::readGtoH(Addr address)
+{
+    if (_tc == NULL) {
+        return PortProxy::readGtoH<T>(TheISA::vtophys(address));
+    } else {
+        return PortProxy::readGtoH<T>(TheISA::vtophys(_tc,address));
+    }
+}
+
+template <typename T>
+void
+FSTranslatingProxy::writeHtoG(Addr address, T data)
+{
+    if (_tc == NULL) {
+        PortProxy::writeHtoG<T>(TheISA::vtophys(address), data);
+    } else {
+        PortProxy::writeHtoG<T>(TheISA::vtophys(_tc,address), data);
+    }
+}
+
+void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
+void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen);
+void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
+
+#endif // __MEM_FS_TRANSLATING_PROXY_HH__
+
diff -r e70d031cb5f9 -r cca29fccc4b1 src/mem/fs_translating_proxy.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/fs_translating_proxy.cc	Mon Nov 28 18:15:15 2011 +0000
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Geza Lore
+ */
+
+#include "base/chunk_generator.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "mem/fs_translating_proxy.hh"
+#include "sim/system.hh"
+
+using namespace TheISA;
+
+FSTranslatingProxy::FSTranslatingProxy(ThreadContext *tc)
+: PortProxy(*(tc->getCpuPtr()->getDataPort())), _tc(tc)
+{
+}
+
+FSTranslatingProxy::FSTranslatingProxy(Port &port)
+: PortProxy(port), _tc(NULL)
+{}
+
+FSTranslatingProxy::FSTranslatingProxy(Port *port)
+: PortProxy(port), _tc(NULL)
+{}
+
+FSTranslatingProxy::~FSTranslatingProxy()
+{}
+
+void
+FSTranslatingProxy::readMem( Addr address, uint8_t* p, int size)
+{
+    Addr paddr;
+    for (ChunkGenerator gen(address, size, TheISA::PageBytes);
+            !gen.done(); gen.next())
+    {
+        if (_tc)
+            paddr = TheISA::vtophys(_tc,gen.addr());
+        else
+            paddr = TheISA::vtophys(gen.addr());
+
+        PortProxy::readMem(paddr, p, gen.size());
+        p += gen.size();
+    }
+}
+
+void
+FSTranslatingProxy::writeMem(Addr address, uint8_t* p, int size)
+{
+    Addr paddr;
+    for (ChunkGenerator gen(address, size, TheISA::PageBytes);
+            !gen.done(); gen.next())
+    {
+        if (_tc)
+            paddr = TheISA::vtophys(_tc,gen.addr());
+        else
+            paddr = TheISA::vtophys(gen.addr());
+
+        PortProxy::writeMem(paddr, p, gen.size());
+        p += gen.size();
+    }
+}
+
+void
+FSTranslatingProxy::setMem(  Addr address, uint8_t  v, int size)
+{
+    Addr paddr;
+    for (ChunkGenerator gen(address, size, TheISA::PageBytes);
+            !gen.done(); gen.next())
+    {
+        if (_tc)
+            paddr = TheISA::vtophys(_tc,gen.addr());
+        else
+            paddr = TheISA::vtophys(gen.addr());
+
+        PortProxy::setMem(paddr, v, gen.size());
+    }
+}
+
+void
+CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
+{
+    uint8_t *dst = (uint8_t *)dest;
+    FSTranslatingProxy *vp = tc->getVirtProxy();
+
+    vp->readMem(src, dst, cplen);
+}
+
+void
+CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
+{
+    uint8_t *src = (uint8_t *)source;
+    FSTranslatingProxy *vp = tc->getVirtProxy();
+
+    vp->writeMem(dest, src, cplen);
+}
+
+void
+CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
+{
+    int len = 0;
+    char *start = dst;
+    FSTranslatingProxy *vp = tc->getVirtProxy();
+
+    do {
+        vp->readMem(vaddr++, (uint8_t*)dst++, 1);
+    } while (len < maxlen && start[len++] != 0 );
+
+    dst[len] = 0;
+}
+
+void
+CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
+{
+    FSTranslatingProxy *vp = tc->getVirtProxy();
+    for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();
+            gen.next())
+    {
+        vp->writeMem(gen.addr(), (uint8_t*)src, gen.size());
+        src += gen.size();
+    }
+}
+
diff -r e70d031cb5f9 -r cca29fccc4b1 src/mem/port_proxy.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/port_proxy.hh	Mon Nov 28 18:15:15 2011 +0000
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Geza Lore
+ */
+
+/**
+ * @file PortProxy Object Declaration. Port proxies are used when non
+ * structural entities need access to the memory system. Proxy objects
+ * replace the previous FunctionalPort, TranslatingPort and VirtualPort
+ * objects, which provided the same functionality as the proxies, but
+ * were instances of ports not corresponding to real structural ports of
+ * the simulated system.
+ * @sa SETranslatingProxy
+ * @sa FSTranslatingProxy
+ */
+
+#ifndef __MEM_PORT_PROXY_HH__
+#define __MEM_PORT_PROXY_HH__
+
+#include "arch/isa_traits.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
+#include "mem/port.hh"
+#include "sim/byteswap.hh"
+
+/**
+ * This object is a proxy for a structural port,
+ * to be used for debug accesses.
+ *
+ * This proxy object is used when non structural entities
+ * (e.g. thread contexts, object file loaders) need access to the
+ * memory system. It calls the corresponding functions on the underlying
+ * structural port, and provides templatized convenience access functions.
+ *
+ * The addresses are interpreted as physical addresses.
+ *
+ * @sa SETranslatingProxy
+ * @sa FSTranslatingProxy
+ */
+class PortProxy
+{
+  protected:
+    Port &_port;
+
+  public:
+    PortProxy(Port &port);
+    PortProxy(Port *port);
+    virtual ~PortProxy();
+
+  public:
+    /**
+     * Read size bytes memory at address and store in p.
+     * @sa MasterPort::readMem
+     */
+    virtual void readMem( Addr address, uint8_t* p, int size);
+
+    /**
+     * Write size bytes from p to address.
+     * @sa MasterPort::writeMem
+     */
+    virtual void writeMem(Addr address, uint8_t* p, int size);
+
+    /**
+     * Fill size bytes starting at addr with byte value val.
+     * @sa MasterPort::setMem
+     */
+    virtual void setMem(  Addr address, uint8_t  v, int size);
+
+    /**
+     * Read sizeof(T) bytes from address and return as object T.
+     */
+    template <typename T>
+    T read(Addr address);
+
+    /**
+     * Write object T to address. Writes sizeof(T) bytes.
+     */
+    template <typename T>
+    void write(Addr address, T data);
+
+    /**
+     * Read sizeof(T) bytes from address and return as object T.
+     * Performs Guest to Host endianness transform.
+     */
+    template <typename T>
+    T readGtoH(Addr address);
+
+    /**
+     * Write object T to address. Writes sizeof(T) bytes.
+     * Performs Host to Guest endianness transform.
+     */
+    template <typename T>
+    void writeHtoG(Addr address, T data);
+};
+
+
+template <typename T>
+T
+PortProxy::read(Addr address)
+{
+    T data;
+    _port.readBlob(address, (uint8_t*)&data, sizeof(T));
+    return data;
+}
+
+template <typename T>
+void
+PortProxy::write(Addr address, T data)
+{
+    _port.writeBlob(address, (uint8_t*)&data, sizeof(T));
+}
+
+template <typename T>
+T
+PortProxy::readGtoH(Addr address)
+{
+    T data;
+    _port.readBlob(address, (uint8_t*)&data, sizeof(T));
+    return TheISA::gtoh(data);
+}
+
+template <typename T>
+void
+PortProxy::writeHtoG(Addr address, T data)
+{
+    data = TheISA::htog(data);
+    _port.writeBlob(address, (uint8_t*)&data, sizeof(T));
+}
+
+#endif // __MEM_PORT_PROXY_HH__
diff -r e70d031cb5f9 -r cca29fccc4b1 src/mem/port_proxy.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/port_proxy.cc	Mon Nov 28 18:15:15 2011 +0000
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Geza Lore
+ */
+
+#include "mem/port_proxy.hh"
+
+PortProxy::PortProxy(Port &port)
+: _port(port)
+{}
+
+PortProxy::PortProxy(Port *port)
+: _port(*port)
+{
+    assert(port != NULL);
+}
+
+PortProxy::~PortProxy()
+{}
+
+void
+PortProxy::readMem( Addr address, uint8_t* p, int size)
+{
+    _port.readBlob(address, p, size);
+}
+
+void
+PortProxy::writeMem(Addr address, uint8_t* p, int size)
+{
+    _port.writeBlob(address, p, size);
+}
+
+void
+PortProxy::setMem(  Addr address, uint8_t  v, int size)
+{
+    _port.memsetBlob(address, v, size);
+}
diff -r e70d031cb5f9 -r cca29fccc4b1 src/mem/se_translating_proxy.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/se_translating_proxy.hh	Mon Nov 28 18:15:15 2011 +0000
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Geza Lore
+ */
+
+/**
+ * @file SETranslatingProxy Object Declaration.
+ * Port proxies are used when non
+ * structural entities need access to the memory system. Proxy objects
+ * replace the previous FunctionalPort, TranslatingPort and VirtualPort
+ * objects, which provided the same functionality as the proxies, but
+ * were instances of ports not corresponding to real structural ports of
+ * the simulated system.
+ * @sa PortProxy
+ * @sa FSTranslatingProxy
+ */
+
+#ifndef __MEM_SE_TRANSLATING_PROXY_HH__
+#define __MEM_SE_TRANSLATING_PROXY_HH__
+
+#include <string>
+
+#include "mem/page_table.hh"
+#include "mem/port_proxy.hh"
+#include "sim/process.hh"
+
+/**
+ * This object is a proxy for a structural port,
+ * to be used for debug accesses in SE mode.
+ *
+ * This proxy object is used when non structural entities
+ * (e.g. thread contexts, object file loaders) need access to the
+ * memory system. It calls the corresponding functions on the underlying
+ * structural port, and provides templatized convenience access functions.
+ *
+ * The addresses are interpreted as virtual addresses, address translation
+ * is performed using the page tables of the process passed at construction.
+ *
+ * @sa PortProxy
+ * @sa FSTranslatingProxy
+ */
+class SETranslatingProxy : public PortProxy
+{
+    /**
+     * @todo: not sure of the exact usage of this, it was migrated from the
+     * transalating ports. Final version should document
+     */
+  public:
+    enum AllocType {
+        Always,
+        Never,
+        NextPage
+    };
+
+  public:
+    SETranslatingProxy(Process *p, AllocType a, Port &port);
+    SETranslatingProxy(Process *p, AllocType a, Port *port);
+    virtual ~SETranslatingProxy();
+
+  private:
+    // helper functions for read/write/set functions
+    bool tryReadMem( Addr address, uint8_t* p, int size);
+    bool tryWriteMem(Addr address, uint8_t* p, int size);
+    bool trySetMem(  Addr address, uint8_t  v, int size);
+
+    bool tryWriteString(Addr addr, const char *str);
+
+  public:
+    // helper function required for syscall emulation
+    bool tryReadString(std::string &str, Addr addr);
+
+  public:
+    /**
+     * Read size bytes memory at address and store in p.
+     * @sa MasterPort::readMem
+     */
+    virtual void readMem( Addr address, uint8_t* p, int size);
+
+    /**
+     * Write size bytes from p to address.
+     * @sa MasterPort::writeMem
+     */
+    virtual void writeMem(Addr address, uint8_t* p, int size);
+
+    /**
+     * Fill size bytes starting at addr with byte value val.
+     * @sa MasterPort::setMem
+     */
+    virtual void setMem(  Addr address, uint8_t  v, int size);
+
+    /**
+     * Read string from address, place into str.
+     */
+    void readString(std::string &str, Addr addr);
+
+    /**
+     * Write string str to address.
+     */
+    void writeString(Addr addr, const char *str);
+
+  private:
+    PageTable *pTable;
+    Process *process;
+    AllocType allocating;
+
+};
+
+#endif // __MEM_SE_TRANSLATING_PROXY_HH__
+
diff -r e70d031cb5f9 -r cca29fccc4b1 src/mem/se_translating_proxy.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/se_translating_proxy.cc	Mon Nov 28 18:15:15 2011 +0000
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Geza Lore
+ */
+
+#include <iostream>
+
+#include "base/chunk_generator.hh"
+#include "mem/se_translating_proxy.hh"
+
+using namespace TheISA;
+
+SETranslatingProxy::SETranslatingProxy(Process *p, AllocType a,
+                                       Port &port)
+: PortProxy(port)
+{
+    assert(p != NULL);
+    pTable      = p->pTable;
+    process     = p;
+    allocating  = a;
+}
+
+SETranslatingProxy::SETranslatingProxy(Process *p, AllocType a,
+                                       Port *port)
+: PortProxy(port)
+{
+    assert(p != NULL);
+    pTable      = p->pTable;
+    process     = p;
+    allocating  = a;
+}
+
+SETranslatingProxy::~SETranslatingProxy()
+{
+}
+
+
+bool
+SETranslatingProxy::tryReadMem(Addr addr, uint8_t *p, int size)
+{
+    Addr paddr;
+    int prevSize = 0;
+
+    for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+
+        if (!pTable->translate(gen.addr(),paddr))
+            return false;
+
+        PortProxy::readMem(paddr, p + prevSize, gen.size());
+        prevSize += gen.size();
+    }
+
+    return true;
+}
+
+bool
+SETranslatingProxy::tryWriteMem(Addr addr, uint8_t *p, int size)
+{
+
+    Addr paddr;
+    int prevSize = 0;
+
+    for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+
+        if (!pTable->translate(gen.addr(), paddr)) {
+            if (allocating == Always) {
+                pTable->allocate(roundDown(gen.addr(), VMPageSize),
+                                 VMPageSize);
+            } else if (allocating == NextPage) {
+                // check if we've accessed the next page on the stack
+                if (!process->fixupStackFault(gen.addr()))
+                    panic("Page table fault when accessing virtual address %#x "
+                            "during functional write\n", gen.addr());
+            } else {
+                return false;
+            }
+            pTable->translate(gen.addr(), paddr);
+        }
+
+        PortProxy::writeMem(paddr, p + prevSize, gen.size());
+        prevSize += gen.size();
+    }
+
+    return true;
+}
+
+bool
+SETranslatingProxy::trySetMem(Addr addr, uint8_t val, int size)
+{
+    Addr paddr;
+
+    for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+
+        if (!pTable->translate(gen.addr(), paddr)) {
+            if (allocating == Always) {
+                pTable->allocate(roundDown(gen.addr(), VMPageSize),
+                                 VMPageSize);
+                pTable->translate(gen.addr(), paddr);
+            } else {
+                return false;
+            }
+        }
+
+        PortProxy::setMem(paddr, val, gen.size());
+    }
+
+    return true;
+}
+
+
+bool
+SETranslatingProxy::tryWriteString(Addr addr, const char *str)
+{
+    Addr paddr,vaddr;
+    uint8_t c;
+
+    vaddr = addr;
+
+    do {
+        c = *str++;
+        if (!pTable->translate(vaddr++,paddr))
+            return false;
+
+        PortProxy::writeMem(paddr, &c, 1);
+    } while (c);
+
+    return true;
+}
+
+bool
+SETranslatingProxy::tryReadString(std::string &str, Addr addr)
+{
+    Addr paddr,vaddr;
+    uint8_t c;
+
+    vaddr = addr;
+
+    do {
+        if (!pTable->translate(vaddr++,paddr))
+            return false;
+
+        PortProxy::readMem(paddr, &c, 1);
+        str += c;
+    } while (c);
+
+    return true;
+}
+
+
+////////////
+
+void
+SETranslatingProxy::readMem( Addr address, uint8_t* p, int size)
+{
+    if(!tryReadMem(address, p, size))
+        fatal("readMem failed at vaddress 0x%x\n",address);
+}
+
+void
+SETranslatingProxy::writeMem(Addr address, uint8_t* p, int size)
+{
+    if(!tryWriteMem(address, p, size))
+        fatal("writeMem failed at vaddress 0x%x\n",address);
+}
+
+void
+SETranslatingProxy::setMem(  Addr address, uint8_t  v, int size)
+{
+    if(!trySetMem(address, v, size))
+        fatal("setMem failed at vaddress 0x%x\n",address);
+}
+
+void
+SETranslatingProxy::writeString(Addr addr, const char *str)
+{
+    if(!tryWriteString(addr, str))
+        fatal("writeString failed at vaddress 0x%x\n", addr);
+}
+
+void
+SETranslatingProxy::readString(std::string &str, Addr addr)
+{
+    if(!tryReadString(str, addr))
+        fatal("readString failed at vaddress 0x%x\n", addr);
+}
+