diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/alpha/linux/process.cc
--- a/src/arch/alpha/linux/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/alpha/linux/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -56,7 +56,7 @@
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "alpha");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
     return 0;
 }
 
@@ -78,7 +78,7 @@
           TypedBufferArg<uint64_t> fpcr(bufPtr);
           // I don't think this exactly matches the HW FPCR
           *fpcr = 0;
-          fpcr.copyOut(tc->getMemPort());
+          fpcr.copyOut(tc->getMemProxy());
           return 0;
       }
 
@@ -106,7 +106,7 @@
       case 14: { // SSI_IEEE_FP_CONTROL
           TypedBufferArg<uint64_t> fpcr(bufPtr);
           // I don't think this exactly matches the HW FPCR
-          fpcr.copyIn(tc->getMemPort());
+          fpcr.copyIn(tc->getMemProxy());
           DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
                    " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
           return 0;
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/alpha/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -37,6 +37,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/Loader.hh"
 #include "mem/page_table.hh"
+#include "mem/se_translating_proxy.hh"
 #include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
@@ -144,16 +145,16 @@
     else
         panic("Unknown int size");
 
-    initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize);
+    initVirtMem->writeMem(stack_min, (uint8_t*)&argc, intSize);
 
     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
     copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
 
     //Copy the aux stuff
     for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
-        initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+        initVirtMem->writeMem(auxv_array_base + x * 2 * intSize,
                 (uint8_t*)&(auxv[x].a_type), intSize);
-        initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+        initVirtMem->writeMem(auxv_array_base + (x * 2 + 1) * intSize,
                 (uint8_t*)&(auxv[x].a_val), intSize);
     }
 
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/alpha/tru64/process.cc
--- a/src/arch/alpha/tru64/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/alpha/tru64/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -55,7 +55,7 @@
     strcpy(name->version, "732");
     strcpy(name->machine, "alpha");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
     return 0;
 }
 
@@ -74,21 +74,21 @@
       case AlphaTru64::GSI_MAX_CPU: {
           TypedBufferArg<uint32_t> max_cpu(bufPtr);
           *max_cpu = htog((uint32_t)process->numCpus());
-          max_cpu.copyOut(tc->getMemPort());
+          max_cpu.copyOut(tc->getMemProxy());
           return 1;
       }
 
       case AlphaTru64::GSI_CPUS_IN_BOX: {
           TypedBufferArg<uint32_t> cpus_in_box(bufPtr);
           *cpus_in_box = htog((uint32_t)process->numCpus());
-          cpus_in_box.copyOut(tc->getMemPort());
+          cpus_in_box.copyOut(tc->getMemProxy());
           return 1;
       }
 
       case AlphaTru64::GSI_PHYSMEM: {
           TypedBufferArg<uint64_t> physmem(bufPtr);
           *physmem = htog((uint64_t)1024 * 1024);  // physical memory in KB
-          physmem.copyOut(tc->getMemPort());
+          physmem.copyOut(tc->getMemProxy());
           return 1;
       }
 
@@ -105,14 +105,14 @@
           infop->cpu_ex_binding = htog(0);
           infop->mhz = htog(667);
 
-          infop.copyOut(tc->getMemPort());
+          infop.copyOut(tc->getMemProxy());
           return 1;
       }
 
       case AlphaTru64::GSI_PROC_TYPE: {
           TypedBufferArg<uint64_t> proc_type(bufPtr);
           *proc_type = htog((uint64_t)11);
-          proc_type.copyOut(tc->getMemPort());
+          proc_type.copyOut(tc->getMemProxy());
           return 1;
       }
 
@@ -121,14 +121,14 @@
           strncpy((char *)bufArg.bufferPtr(),
                   "COMPAQ Professional Workstation XP1000",
                   nbytes);
-          bufArg.copyOut(tc->getMemPort());
+          bufArg.copyOut(tc->getMemProxy());
           return 1;
       }
 
       case AlphaTru64::GSI_CLK_TCK: {
           TypedBufferArg<uint64_t> clk_hz(bufPtr);
           *clk_hz = htog((uint64_t)1024);
-          clk_hz.copyOut(tc->getMemPort());
+          clk_hz.copyOut(tc->getMemProxy());
           return 1;
       }
 
@@ -193,7 +193,7 @@
           elp->si_phz = htog(clk_hz);
           elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch?
           elp->si_max_procs = htog(process->numCpus());
-          elp.copyOut(tc->getMemPort());
+          elp.copyOut(tc->getMemProxy());
           return 0;
       }
 
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/arm/linux/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -70,7 +70,7 @@
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "armv7l");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
     return 0;
 }
 
@@ -452,7 +452,7 @@
     int index = 0;
     uint32_t tlsPtr = process->getSyscallArg(tc, index);
 
-    tc->getMemPort()->writeBlob(ArmLinuxProcess::commPage + 0x0ff0,
+    tc->getMemProxy()->writeMem(ArmLinuxProcess::commPage + 0x0ff0,
                                 (uint8_t *)&tlsPtr, sizeof(tlsPtr));
     tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
     return 0;
@@ -512,7 +512,7 @@
 
     // Fill this page with swi -1 so we'll no if we land in it somewhere.
     for (Addr addr = 0; addr < PageBytes; addr += sizeof(swiNeg1)) {
-        tc->getMemPort()->writeBlob(commPage + addr,
+        tc->getMemProxy()->writeMem(commPage + addr,
                                     swiNeg1, sizeof(swiNeg1));
     }
 
@@ -521,7 +521,7 @@
         0x5f, 0xf0, 0x7f, 0xf5, // dmb
         0x0e, 0xf0, 0xa0, 0xe1  // return
     };
-    tc->getMemPort()->writeBlob(commPage + 0x0fa0, memory_barrier,
+    tc->getMemProxy()->writeMem(commPage + 0x0fa0, memory_barrier,
                                 sizeof(memory_barrier));
 
     uint8_t cmpxchg[] =
@@ -535,7 +535,7 @@
         0x5f, 0xf0, 0x7f, 0xf5,  // dmb
         0x0e, 0xf0, 0xa0, 0xe1   // return
     };
-    tc->getMemPort()->writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
+    tc->getMemProxy()->writeMem(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
 
     uint8_t get_tls[] =
     {
@@ -543,7 +543,7 @@
         0x70, 0x0f, 0x1d, 0xee, // mrc p15, 0, r0, c13, c0, 3
         0x0e, 0xf0, 0xa0, 0xe1  // return
     };
-    tc->getMemPort()->writeBlob(commPage + 0x0fe0, get_tls, sizeof(get_tls));
+    tc->getMemProxy()->writeMem(commPage + 0x0fe0, get_tls, sizeof(get_tls));
 }
 
 ArmISA::IntReg
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/arm/process.cc
--- a/src/arch/arm/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/arm/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -285,7 +285,7 @@
 
     //Write out the sentry void *
     uint32_t sentry_NULL = 0;
-    initVirtMem->writeBlob(sentry_base,
+    initVirtMem->writeMem(sentry_base,
             (uint8_t*)&sentry_NULL, sentry_size);
 
     //Fix up the aux vectors which point to other data
@@ -305,20 +305,20 @@
     //Copy the aux stuff
     for(int x = 0; x < auxv.size(); x++)
     {
-        initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+        initVirtMem->writeMem(auxv_array_base + x * 2 * intSize,
                 (uint8_t*)&(auxv[x].a_type), intSize);
-        initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+        initVirtMem->writeMem(auxv_array_base + (x * 2 + 1) * intSize,
                 (uint8_t*)&(auxv[x].a_val), intSize);
     }
     //Write out the terminating zeroed auxilliary vector
     const uint64_t zero = 0;
-    initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
+    initVirtMem->writeMem(auxv_array_base + 2 * intSize * auxv.size(),
             (uint8_t*)&zero, 2 * intSize);
 
     copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
 
-    initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
+    initVirtMem->writeMem(argc_base, (uint8_t*)&guestArgc, intSize);
 
     ThreadContext *tc = system->getThreadContext(contextIds[0]);
     //Set the stack pointer register
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/mips/linux/process.cc
--- a/src/arch/mips/linux/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/mips/linux/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -59,7 +59,7 @@
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "mips");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
     return 0;
 }
 
@@ -82,7 +82,7 @@
             TypedBufferArg<uint64_t> fpcr(bufPtr);
             // I don't think this exactly matches the HW FPCR
             *fpcr = 0;
-            fpcr.copyOut(tc->getMemPort());
+            fpcr.copyOut(tc->getMemProxy());
             return 0;
         }
       default:
@@ -111,7 +111,7 @@
             // SSI_IEEE_FP_CONTROL
             TypedBufferArg<uint64_t> fpcr(bufPtr);
             // I don't think this exactly matches the HW FPCR
-            fpcr.copyIn(tc->getMemPort());
+            fpcr.copyIn(tc->getMemProxy());
             DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): "
                    " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
             return 0;
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/mips/process.cc
--- a/src/arch/mips/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/mips/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -150,7 +150,7 @@
 
     argc = htog((IntType)argc);
 
-    initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize);
+    initVirtMem->writeMem(stack_min, (uint8_t*)&argc, intSize);
 
     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
 
@@ -158,9 +158,9 @@
 
     // Copy the aux vector
     for (typename vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
-        initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+        initVirtMem->writeMem(auxv_array_base + x * 2 * intSize,
                 (uint8_t*)&(auxv[x].a_type), intSize);
-        initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+        initVirtMem->writeMem(auxv_array_base + (x * 2 + 1) * intSize,
                 (uint8_t*)&(auxv[x].a_val), intSize);
     }
 
@@ -168,7 +168,7 @@
     for (unsigned i = 0; i < 2; i++) {
         const IntType zero = 0;
         const Addr addr = auxv_array_base + 2 * intSize * (auxv.size() + i);
-        initVirtMem->writeBlob(addr, (uint8_t*)&zero, intSize);
+        initVirtMem->writeMem(addr, (uint8_t*)&zero, intSize);
     }
 
     ThreadContext *tc = system->getThreadContext(contextIds[0]);
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/power/linux/process.cc
--- a/src/arch/power/linux/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/power/linux/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -59,7 +59,7 @@
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "power");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
     return 0;
 }
 
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/power/process.cc
--- a/src/arch/power/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/power/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -219,7 +219,7 @@
 
     //Write out the sentry void *
     uint32_t sentry_NULL = 0;
-    initVirtMem->writeBlob(sentry_base,
+    initVirtMem->writeMem(sentry_base,
             (uint8_t*)&sentry_NULL, sentry_size);
 
     //Fix up the aux vectors which point to other data
@@ -236,20 +236,20 @@
     //Copy the aux stuff
     for (int x = 0; x < auxv.size(); x++)
     {
-        initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+        initVirtMem->writeMem(auxv_array_base + x * 2 * intSize,
                 (uint8_t*)&(auxv[x].a_type), intSize);
-        initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+        initVirtMem->writeMem(auxv_array_base + (x * 2 + 1) * intSize,
                 (uint8_t*)&(auxv[x].a_val), intSize);
     }
     //Write out the terminating zeroed auxilliary vector
     const uint64_t zero = 0;
-    initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
+    initVirtMem->writeMem(auxv_array_base + 2 * intSize * auxv.size(),
             (uint8_t*)&zero, 2 * intSize);
 
     copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
 
-    initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
+    initVirtMem->writeMem(argc_base, (uint8_t*)&guestArgc, intSize);
 
     ThreadContext *tc = system->getThreadContext(contextIds[0]);
 
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/sparc/linux/syscalls.cc
--- a/src/arch/sparc/linux/syscalls.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/sparc/linux/syscalls.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -50,7 +50,7 @@
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "sparc");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
 
     return 0;
 }
@@ -69,19 +69,19 @@
     if (ruid) {
         BufferArg ruidBuff(ruid, sizeof(IntReg));
         memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg));
-        ruidBuff.copyOut(tc->getMemPort());
+        ruidBuff.copyOut(tc->getMemProxy());
     }
     // Set the euid
     if (euid) {
         BufferArg euidBuff(euid, sizeof(IntReg));
         memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg));
-        euidBuff.copyOut(tc->getMemPort());
+        euidBuff.copyOut(tc->getMemProxy());
     }
     // Set the suid
     if (suid) {
         BufferArg suidBuff(suid, sizeof(IntReg));
         memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg));
-        suidBuff.copyOut(tc->getMemPort());
+        suidBuff.copyOut(tc->getMemProxy());
     }
     return 0;
 }
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/sparc/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -355,7 +355,7 @@
 
     // Write out the sentry void *
     uint64_t sentry_NULL = 0;
-    initVirtMem->writeBlob(sentry_base,
+    initVirtMem->writeMem(sentry_base,
             (uint8_t*)&sentry_NULL, sentry_size);
 
     // Write the file name
@@ -363,23 +363,23 @@
 
     // Copy the aux stuff
     for (int x = 0; x < auxv.size(); x++) {
-        initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+        initVirtMem->writeMem(auxv_array_base + x * 2 * intSize,
                 (uint8_t*)&(auxv[x].a_type), intSize);
-        initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+        initVirtMem->writeMem(auxv_array_base + (x * 2 + 1) * intSize,
                 (uint8_t*)&(auxv[x].a_val), intSize);
     }
 
     // Write out the terminating zeroed auxilliary vector
     const IntType zero = 0;
-    initVirtMem->writeBlob(auxv_array_base + intSize * 2 * auxv.size(),
+    initVirtMem->writeMem(auxv_array_base + intSize * 2 * auxv.size(),
             (uint8_t*)&zero, intSize);
-    initVirtMem->writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1),
+    initVirtMem->writeMem(auxv_array_base + intSize * (2 * auxv.size() + 1),
             (uint8_t*)&zero, intSize);
 
     copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
 
-    initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
+    initVirtMem->writeMem(argc_base, (uint8_t*)&guestArgc, intSize);
 
     // Set up space for the trap handlers into the processes address space.
     // Since the stack grows down and there is reserved address space abov
@@ -412,9 +412,9 @@
     SparcLiveProcess::argsInit<uint64_t>(pageSize);
 
     // Stuff the trap handlers into the process address space
-    initVirtMem->writeBlob(fillStart,
+    initVirtMem->writeMem(fillStart,
             (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts);
-    initVirtMem->writeBlob(spillStart,
+    initVirtMem->writeMem(spillStart,
             (uint8_t*)spillHandler64, sizeof(MachInst) *  numSpillInsts);
 }
 
@@ -424,9 +424,9 @@
     SparcLiveProcess::argsInit<uint32_t>(pageSize);
 
     // Stuff the trap handlers into the process address space
-    initVirtMem->writeBlob(fillStart,
+    initVirtMem->writeMem(fillStart,
             (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts);
-    initVirtMem->writeBlob(spillStart,
+    initVirtMem->writeMem(spillStart,
             (uint8_t*)spillHandler32, sizeof(MachInst) *  numSpillInsts);
 }
 
@@ -448,7 +448,7 @@
             for (int index = 16; index < 32; index++) {
                 uint32_t regVal = tc->readIntReg(index);
                 regVal = htog(regVal);
-                if (!tc->getMemPort()->tryWriteBlob(
+                if (!tc->getMemProxy()->tryWriteMem(
                         sp + (index - 16) * 4, (uint8_t *)&regVal, 4)) {
                     warn("Failed to save register to the stack when "
                             "flushing windows.\n");
@@ -483,7 +483,7 @@
             for (int index = 16; index < 32; index++) {
                 IntReg regVal = tc->readIntReg(index);
                 regVal = htog(regVal);
-                if (!tc->getMemPort()->tryWriteBlob(
+                if (!tc->getMemProxy()->tryWriteMem(
                         sp + 2047 + (index - 16) * 8, (uint8_t *)&regVal, 8)) {
                     warn("Failed to save register to the stack when "
                             "flushing windows.\n");
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/sparc/solaris/process.cc
--- a/src/arch/sparc/solaris/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/sparc/solaris/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -55,7 +55,7 @@
     strcpy(name->version, "Generic_118558-21");
     strcpy(name->machine, "sun4u");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
 
     return 0;
 }
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/x86/linux/syscalls.cc
--- a/src/arch/x86/linux/syscalls.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/x86/linux/syscalls.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -59,7 +59,7 @@
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "x86_64");
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
 
     return 0;
 }
@@ -81,7 +81,7 @@
     int code = process->getSyscallArg(tc, index);
     uint64_t addr = process->getSyscallArg(tc, index);
     uint64_t fsBase, gsBase;
-    TranslatingPort *p = tc->getMemPort();
+    SETranslatingProxy *p = tc->getMemProxy();
     switch(code)
     {
       //Each of these valid options should actually check addr.
@@ -149,10 +149,10 @@
         gdt(x86lp->gdtStart() + minTLSEntry * sizeof(uint64_t),
                 numTLSEntries * sizeof(uint64_t));
 
-    if (!userDesc.copyIn(tc->getMemPort()))
+    if (!userDesc.copyIn(tc->getMemProxy()))
         return -EFAULT;
 
-    if (!gdt.copyIn(tc->getMemPort()))
+    if (!gdt.copyIn(tc->getMemProxy()))
         panic("Failed to copy in GDT for %s.\n", desc->name);
 
     if (userDesc->entry_number == (uint32_t)(-1)) {
@@ -204,9 +204,9 @@
 
     gdt[index] = (uint64_t)segDesc;
 
-    if (!userDesc.copyOut(tc->getMemPort()))
+    if (!userDesc.copyOut(tc->getMemProxy()))
         return -EFAULT;
-    if (!gdt.copyOut(tc->getMemPort()))
+    if (!gdt.copyOut(tc->getMemProxy()))
         panic("Failed to copy out GDT for %s.\n", desc->name);
 
     return 0;
diff -r cca29fccc4b1 -r a976ceb6edd7 src/arch/x86/process.cc
--- a/src/arch/x86/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/arch/x86/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -173,7 +173,7 @@
         0x0f,0x05,                             // syscall
         0xc3                                   // retq
     };
-    initVirtMem->writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
+    initVirtMem->writeMem(vsyscallPage.base + vsyscallPage.vtimeOffset,
             vtimeBlob, sizeof(vtimeBlob));
 
     uint8_t vgettimeofdayBlob[] = {
@@ -181,7 +181,7 @@
         0x0f,0x05,                             // syscall
         0xc3                                   // retq
     };
-    initVirtMem->writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
+    initVirtMem->writeMem(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
             vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
 
     for (int i = 0; i < contextIds.size(); i++) {
@@ -282,7 +282,7 @@
         0x89, 0xe5, // mov %esp, %ebp
         0x0f, 0x34  // sysenter
     };
-    initVirtMem->writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
+    initVirtMem->writeMem(vsyscallPage.base + vsyscallPage.vsyscallOffset,
             vsyscallBlob, sizeof(vsyscallBlob));
 
     uint8_t vsysexitBlob[] = {
@@ -291,7 +291,7 @@
         0x59,       // pop %ecx
         0xc3        // ret
     };
-    initVirtMem->writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
+    initVirtMem->writeMem(vsyscallPage.base + vsyscallPage.vsysexitOffset,
             vsysexitBlob, sizeof(vsysexitBlob));
 
     for (int i = 0; i < contextIds.size(); i++) {
@@ -609,7 +609,7 @@
 
     //Write out the sentry void *
     IntType sentry_NULL = 0;
-    initVirtMem->writeBlob(sentry_base,
+    initVirtMem->writeMem(sentry_base,
             (uint8_t*)&sentry_NULL, sentry_size);
 
     //Write the file name
@@ -626,14 +626,14 @@
     //Copy the aux stuff
     for(int x = 0; x < auxv.size(); x++)
     {
-        initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+        initVirtMem->writeMem(auxv_array_base + x * 2 * intSize,
                 (uint8_t*)&(auxv[x].a_type), intSize);
-        initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+        initVirtMem->writeMem(auxv_array_base + (x * 2 + 1) * intSize,
                 (uint8_t*)&(auxv[x].a_val), intSize);
     }
     //Write out the terminating zeroed auxilliary vector
     const uint64_t zero = 0;
-    initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
+    initVirtMem->writeMem(auxv_array_base + 2 * intSize * auxv.size(),
             (uint8_t*)&zero, 2 * intSize);
 
     initVirtMem->writeString(aux_data_base, platform.c_str());
@@ -641,7 +641,7 @@
     copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
 
-    initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
+    initVirtMem->writeMem(argc_base, (uint8_t*)&guestArgc, intSize);
 
     ThreadContext *tc = system->getThreadContext(contextIds[0]);
     //Set the stack pointer register
diff -r cca29fccc4b1 -r a976ceb6edd7 src/base/loader/object_file.hh
--- a/src/base/loader/object_file.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/base/loader/object_file.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -38,6 +38,7 @@
 #include "base/types.hh"
 
 class Port;
+class PortProxy;
 class SymbolTable;
 
 class ObjectFile
@@ -85,6 +86,8 @@
 
     virtual bool loadSections(Port *memPort, Addr addrMask =
             std::numeric_limits<Addr>::max());
+    virtual bool loadSections(PortProxy *memProxy, Addr addrMask =
+            std::numeric_limits<Addr>::max());
     virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask =
             std::numeric_limits<Addr>::max()) = 0;
     virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask =
@@ -112,6 +115,7 @@
     Section bss;
 
     bool loadSection(Section *sec, Port *memPort, Addr addrMask);
+    bool loadSection(Section *sec, PortProxy *memProxy, Addr addrMask);
     void setGlobalPointer(Addr global_ptr) { globalPtr = global_ptr; }
 
   public:
diff -r cca29fccc4b1 -r a976ceb6edd7 src/base/loader/object_file.cc
--- a/src/base/loader/object_file.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/base/loader/object_file.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -46,6 +46,7 @@
 #include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
 #include "mem/translating_port.hh"
+#include "mem/port_proxy.hh"
 
 using namespace std;
 
@@ -80,6 +81,21 @@
     return true;
 }
 
+bool
+ObjectFile::loadSection(Section *sec, PortProxy *memProxy, Addr addrMask)
+{
+    if (sec->size != 0) {
+        Addr addr = sec->baseAddr & addrMask;
+        if (sec->fileImage) {
+            memProxy->writeMem(addr, sec->fileImage, sec->size);
+        }
+        else {
+            // no image: must be bss
+            memProxy->setMem(addr, 0, sec->size);
+        }
+    }
+    return true;
+}
 
 bool
 ObjectFile::loadSections(Port *memPort, Addr addrMask)
@@ -89,6 +105,13 @@
             && loadSection(&bss, memPort, addrMask));
 }
 
+bool
+ObjectFile::loadSections(PortProxy *memProxy, Addr addrMask)
+{
+    return (loadSection(&text, memProxy, addrMask)
+            && loadSection(&data, memProxy, addrMask)
+            && loadSection(&bss, memProxy, addrMask));
+}
 
 void
 ObjectFile::close()
diff -r cca29fccc4b1 -r a976ceb6edd7 src/base/remote_gdb.cc
--- a/src/base/remote_gdb.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/base/remote_gdb.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -138,7 +138,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/GDBAll.hh"
 #include "mem/port.hh"
-#include "mem/translating_port.hh"
+#include "mem/se_translating_proxy.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -466,10 +466,11 @@
 
 #if FULL_SYSTEM
     VirtualPort *port = context->getVirtPort();
+    port->readBlob(vaddr, (uint8_t*)data, size);
 #else
-    TranslatingPort *port = context->getMemPort();
+    SETranslatingProxy *port = context->getMemProxy();
+    port->readMem(vaddr, (uint8_t*)data, size);
 #endif
-    port->readBlob(vaddr, (uint8_t*)data, size);
 
 #if TRACING_ON
     if (DTRACE(GDBRead)) {
@@ -508,10 +509,11 @@
     }
 #if FULL_SYSTEM
     VirtualPort *port = context->getVirtPort();
+    port->writeBlob(vaddr, (uint8_t*)data, size);
 #else
-    TranslatingPort *port = context->getMemPort();
+    SETranslatingProxy *port = context->getMemProxy();
+    port->writeMem(vaddr, (uint8_t*)data, size);
 #endif
-    port->writeBlob(vaddr, (uint8_t*)data, size);
 #if !FULL_SYSTEM
     delete port;
 #endif
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/checker/thread_context.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -102,7 +102,7 @@
     VirtualPort *getVirtPort()
     { return actualTC->getVirtPort(); }
 #else
-    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+    SETranslatingProxy *getMemProxy() { return actualTC->getMemProxy(); }
 
     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 #endif
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/inorder/thread_context.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -44,7 +44,7 @@
     class Statistics;
 };
 
-class TranslatingPort;
+class SETranslatingProxy;
 
 /**
  * Derived ThreadContext class for use with the InOrderCPU.  It
@@ -147,7 +147,7 @@
         return this->thread->quiesceEvent;
     }
 #else
-    TranslatingPort *getMemPort() { return thread->getMemPort(); }
+    SETranslatingProxy *getMemProxy() { return thread->getMemProxy(); }
 
     /** Returns a pointer to this thread's process. */
     Process *getProcessPtr() { return thread->getProcessPtr(); }
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/o3/thread_context.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -40,7 +40,7 @@
     class Statistics;
 };
 
-class TranslatingPort;
+class SETranslatingProxy;
 
 /**
  * Derived ThreadContext class for use with the O3CPU.  It
@@ -103,7 +103,7 @@
 
     virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
 #else
-    virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
+    virtual SETranslatingProxy *getMemProxy() { return thread->getMemProxy(); }
 
     /** Returns a pointer to this thread's process. */
     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/ozone/cpu.hh
--- a/src/cpu/ozone/cpu.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/ozone/cpu.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -129,7 +129,7 @@
         VirtualPort *getVirtPort()
         { return thread->getVirtPort(); }
 #else
-        TranslatingPort *getMemPort() { return thread->getMemPort(); }
+        SETranslatingProxy *getMemProxy() { return thread->getMemProxy(); }
 
         Process *getProcessPtr() { return thread->getProcessPtr(); }
 #endif
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/simple_thread.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -71,7 +71,7 @@
 
 #include "mem/page_table.hh"
 #include "sim/process.hh"
-class TranslatingPort;
+class SETranslatingProxy;
 
 #endif // FULL_SYSTEM
 
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/thread_context.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -50,7 +50,7 @@
 class Checkpoint;
 class Decoder;
 class EndQuiesceEvent;
-class TranslatingPort;
+class SETranslatingProxy;
 class FunctionalPort;
 class VirtualPort;
 class Process;
@@ -134,7 +134,7 @@
 
     virtual void connectMemPorts(ThreadContext *tc) = 0;
 #else
-    virtual TranslatingPort *getMemPort() = 0;
+    virtual SETranslatingProxy *getMemProxy() = 0;
 
     virtual Process *getProcessPtr() = 0;
 #endif
@@ -304,7 +304,7 @@
 
     void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
 #else
-    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+    SETranslatingProxy *getMemProxy() { return actualTC->getMemProxy(); }
 
     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 #endif
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/thread_state.hh
--- a/src/cpu/thread_state.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/thread_state.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -55,7 +55,7 @@
 
 class Checkpoint;
 class Port;
-class TranslatingPort;
+class SETranslatingProxy;
 
 /**
  *  Struct for holding general thread state that is needed across CPU
@@ -117,9 +117,9 @@
 #else
     Process *getProcessPtr() { return process; }
 
-    TranslatingPort *getMemPort();
+    SETranslatingProxy *getMemProxy();
 
-    void setMemPort(TranslatingPort *_port) { port = _port; }
+    void setMemProxy(SETranslatingProxy *_port) { port = _port; }
 #endif
 
     /** Reads the number of instructions functionally executed and
@@ -194,7 +194,7 @@
      * addresses. */
     VirtualPort *virtPort;
 #else
-    TranslatingPort *port;
+    SETranslatingProxy *port;
 
     Process *process;
 #endif
diff -r cca29fccc4b1 -r a976ceb6edd7 src/cpu/thread_state.cc
--- a/src/cpu/thread_state.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/cpu/thread_state.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -33,7 +33,7 @@
 #include "cpu/profile.hh"
 #include "cpu/thread_state.hh"
 #include "mem/port.hh"
-#include "mem/translating_port.hh"
+#include "mem/se_translating_proxy.hh"
 #include "sim/serialize.hh"
 
 #if FULL_SYSTEM
@@ -63,7 +63,6 @@
 {
 #if !FULL_SYSTEM
     if (port) {
-        delete port->getPeer();
         delete port;
     }
 #endif
@@ -155,17 +154,17 @@
 }
 
 #else
-TranslatingPort *
-ThreadState::getMemPort()
+SETranslatingProxy *
+ThreadState::getMemProxy()
 {
     if (port != NULL)
         return port;
 
-    /* Use this port to for syscall emulation writes to memory. */
-    port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), _threadId),
-                               process, TranslatingPort::NextPage);
+    /* Use this port proxy to for syscall emulation writes to memory. */
+    port = new SETranslatingProxy(process, SETranslatingProxy::NextPage,
+                                    process->systemPort());
 
-    connectToMemFunc(port);
+//    connectToMemFunc(port);
 
     return port;
 }
diff -r cca29fccc4b1 -r a976ceb6edd7 src/kern/solaris/solaris.hh
--- a/src/kern/solaris/solaris.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/kern/solaris/solaris.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -42,8 +42,6 @@
 
 #include "kern/operatingsystem.hh"
 
-class TranslatingPort;
-
 ///
 /// This class encapsulates the types, structures, constants,
 /// functions, and syscall-number mappings specific to the Solaris
diff -r cca29fccc4b1 -r a976ceb6edd7 src/kern/tru64/tru64.hh
--- a/src/kern/tru64/tru64.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/kern/tru64/tru64.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -69,7 +69,7 @@
 typedef struct statfs global_statfs;
 typedef struct dirent global_dirent;
 
-class TranslatingPort;
+class SETranslatingProxy;
 
 ///
 /// This class encapsulates the types, structures, constants,
@@ -404,7 +404,7 @@
     /// memory space.  Used by statfs() and fstatfs().
     template <class T>
     static void
-    copyOutStatfsBuf(TranslatingPort *mem, Addr addr, global_statfs *host)
+    copyOutStatfsBuf(SETranslatingProxy *mem, Addr addr, global_statfs *host)
     {
         using namespace TheISA;
 
@@ -453,7 +453,7 @@
 
         // just pass basep through uninterpreted.
         TypedBufferArg<int64_t> basep(tgt_basep);
-        basep.copyIn(tc->getMemPort());
+        basep.copyIn(tc->getMemProxy());
         long host_basep = (off_t)htog((int64_t)*basep);
         int host_result = getdirentries(fd, host_buf, tgt_nbytes, &host_basep);
 
@@ -480,7 +480,7 @@
             tgt_dp->d_reclen = tgt_bufsize;
             tgt_dp->d_namlen = namelen;
             strcpy(tgt_dp->d_name, host_dp->d_name);
-            tgt_dp.copyOut(tc->getMemPort());
+            tgt_dp.copyOut(tc->getMemProxy());
 
             tgt_buf_ptr += tgt_bufsize;
             host_buf_ptr += host_dp->d_reclen;
@@ -489,7 +489,7 @@
         delete [] host_buf;
 
         *basep = htog((int64_t)host_basep);
-        basep.copyOut(tc->getMemPort());
+        basep.copyOut(tc->getMemProxy());
 
         return tgt_buf_ptr - tgt_buf;
 #endif
@@ -505,7 +505,7 @@
         int index = 0;
         TypedBufferArg<Tru64::sigcontext> sc(process->getSyscallArg(tc, index));
 
-        sc.copyIn(tc->getMemPort());
+        sc.copyIn(tc->getMemProxy());
 
         // Restore state from sigcontext structure.
         // Note that we'll advance PC <- NPC before the end of the cycle,
@@ -540,7 +540,7 @@
         int index = 0;
         TypedBufferArg<Tru64::vm_stack> argp(process->getSyscallArg(tc, index));
 
-        argp.copyIn(tc->getMemPort());
+        argp.copyIn(tc->getMemProxy());
 
         int stack_size =
             gtoh(argp->rsize) + gtoh(argp->ysize) + gtoh(argp->gsize);
@@ -567,7 +567,7 @@
         process->allocateMem(rounded_stack_base, rounded_stack_size);
 
         argp->address = gtoh(rounded_stack_base);
-        argp.copyOut(tc->getMemPort());
+        argp.copyOut(tc->getMemProxy());
 
         return 0;
     }
@@ -591,7 +591,7 @@
             attrp(process->getSyscallArg(tc, index));
         TypedBufferArg<Addr> configptr_ptr(process->getSyscallArg(tc, index));
 
-        attrp.copyIn(tc->getMemPort());
+        attrp.copyIn(tc->getMemProxy());
 
         if (gtoh(attrp->nxm_version) != NXM_LIB_VERSION) {
             cerr << "nxm_task_init: thread library version mismatch! "
@@ -685,10 +685,10 @@
         int size = cur_addr - base_addr;
         process->allocateMem(base_addr, roundUp(size, VMPageSize));
 
-        config.copyOut(tc->getMemPort());
-        slot_state.copyOut(tc->getMemPort());
-        rad_state.copyOut(tc->getMemPort());
-        configptr_ptr.copyOut(tc->getMemPort());
+        config.copyOut(tc->getMemProxy());
+        slot_state.copyOut(tc->getMemProxy());
+        rad_state.copyOut(tc->getMemProxy());
+        configptr_ptr.copyOut(tc->getMemProxy());
 
         return 0;
     }
@@ -727,7 +727,7 @@
         int thread_index = process->getSyscallArg(tc, index);
 
         // get attribute args
-        attrp.copyIn(tc->getMemPort());
+        attrp.copyIn(tc->getMemProxy());
 
         if (gtoh(attrp->version) != NXM_LIB_VERSION) {
             cerr << "nxm_thread_create: thread library version mismatch! "
@@ -752,7 +752,7 @@
 
         TypedBufferArg<Tru64::nxm_shared> rad_state(0x14000,
                                                     rad_state_size);
-        rad_state.copyIn(tc->getMemPort());
+        rad_state.copyIn(tc->getMemProxy());
 
         uint64_t uniq_val = gtoh(attrp->pthid) - gtoh(rad_state->nxm_uniq_offset);
 
@@ -763,7 +763,7 @@
 
             // This is supposed to be a port number.  Make something up.
             *kidp = htog(99);
-            kidp.copyOut(tc->getMemPort());
+            kidp.copyOut(tc->getMemProxy());
 
             return 0;
         } else if (gtoh(attrp->type) == Tru64::NXM_TYPE_VP) {
@@ -777,7 +777,7 @@
             ssp->nxm_u.pth_id = attrp->pthid;
             ssp->nxm_u.nxm_active = htog(uniq_val | 1);
 
-            rad_state.copyOut(tc->getMemPort());
+            rad_state.copyOut(tc->getMemProxy());
 
             Addr slot_state_addr = 0x12000 + sizeof(Tru64::nxm_config_info);
             int slot_state_size =
@@ -787,7 +787,7 @@
                 slot_state(slot_state_addr,
                            slot_state_size);
 
-            slot_state.copyIn(tc->getMemPort());
+            slot_state.copyIn(tc->getMemProxy());
 
             if (slot_state[thread_index] != Tru64::NXM_SLOT_AVAIL) {
                 cerr << "nxm_thread_createFunc: requested VP slot "
@@ -799,7 +799,7 @@
             // doesn't work anyway
             slot_state[thread_index] = Tru64::NXM_SLOT_BOUND;
 
-            slot_state.copyOut(tc->getMemPort());
+            slot_state.copyOut(tc->getMemProxy());
 
             // Find a free simulator thread context.
             ThreadContext *tc = process->findFreeContext();
@@ -811,7 +811,7 @@
                 // and get away with just sticking the thread index
                 // here.
                 *kidp = htog(thread_index);
-                kidp.copyOut(tc->getMemPort());
+                kidp.copyOut(tc->getMemProxy());
 
                 return 0;
             }
@@ -952,12 +952,12 @@
 
         TypedBufferArg<uint64_t> lockp(uaddr);
 
-        lockp.copyIn(tc->getMemPort());
+        lockp.copyIn(tc->getMemProxy());
 
         if (gtoh(*lockp) == 0) {
             // lock is free: grab it
             *lockp = htog(1);
-            lockp.copyOut(tc->getMemPort());
+            lockp.copyOut(tc->getMemProxy());
         } else {
             // lock is busy: disable until free
             process->waitList.push_back(Process::WaitRec(uaddr, tc));
@@ -971,7 +971,7 @@
     {
         TypedBufferArg<uint64_t> lockp(uaddr);
 
-        lockp.copyIn(tc->getMemPort());
+        lockp.copyIn(tc->getMemProxy());
         assert(*lockp != 0);
 
         // Check for a process waiting on the lock.
@@ -980,7 +980,7 @@
         // clear lock field if no waiting context is taking over the lock
         if (num_waiting == 0) {
             *lockp = 0;
-            lockp.copyOut(tc->getMemPort());
+            lockp.copyOut(tc->getMemProxy());
         }
     }
 
@@ -1011,12 +1011,12 @@
         Addr uaddr = process->getSyscallArg(tc, index);
         TypedBufferArg<uint64_t> lockp(uaddr);
 
-        lockp.copyIn(tc->getMemPort());
+        lockp.copyIn(tc->getMemProxy());
 
         if (gtoh(*lockp) == 0) {
             // lock is free: grab it
             *lockp = htog(1);
-            lockp.copyOut(tc->getMemPort());
+            lockp.copyOut(tc->getMemProxy());
             return 0;
         } else {
             return 1;
@@ -1077,7 +1077,7 @@
         TypedBufferArg<uint64_t> lockp(lock_addr);
 
         // user is supposed to acquire lock before entering
-        lockp.copyIn(tc->getMemPort());
+        lockp.copyIn(tc->getMemProxy());
         assert(gtoh(*lockp) != 0);
 
         m5_unlock_mutex(lock_addr, process, tc);
@@ -1166,13 +1166,13 @@
 
     typedef F64_stat tgt_stat;
 /*
-    static void copyOutStatBuf(TranslatingPort *mem, Addr addr,
+    static void copyOutStatBuf(SETranslatingProxy *mem, Addr addr,
                                global_stat *host)
     {
         Tru64::copyOutStatBuf<Tru64::F64_stat>(mem, addr, host);
     }*/
 
-    static void copyOutStatfsBuf(TranslatingPort *mem, Addr addr,
+    static void copyOutStatfsBuf(SETranslatingProxy *mem, Addr addr,
                                  global_statfs *host)
     {
         Tru64::copyOutStatfsBuf<Tru64::F64_statfs>(mem, addr, host);
@@ -1212,13 +1212,13 @@
 
     typedef pre_F64_stat tgt_stat;
 /*
-    static void copyOutStatBuf(TranslatingPort *mem, Addr addr,
+    static void copyOutStatBuf(SETranslatingProxy *mem, Addr addr,
                                global_stat *host)
     {
         Tru64::copyOutStatBuf<Tru64::pre_F64_stat>(mem, addr, host);
     }*/
 
-    static void copyOutStatfsBuf(TranslatingPort *mem, Addr addr,
+    static void copyOutStatfsBuf(SETranslatingProxy *mem, Addr addr,
                                  global_statfs *host)
     {
         Tru64::copyOutStatfsBuf<Tru64::pre_F64_statfs>(mem, addr, host);
diff -r cca29fccc4b1 -r a976ceb6edd7 src/mem/SConscript
--- a/src/mem/SConscript	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/mem/SConscript	Mon Nov 28 18:17:05 2011 +0000
@@ -42,12 +42,15 @@
 Source('tport.cc')
 Source('mport.cc')
 
+
 Source('port_proxy.cc')
 
-if env['FULL_SYSTEM']:
-    Source('fs_translating_proxy.cc')
-else:
-    Source('se_translating_proxy.cc')
+if env['TARGET_ISA'] != 'no':
+    if env['FULL_SYSTEM']:
+        #Source('fs_translating_proxy.cc')
+        pass
+    else:
+        Source('se_translating_proxy.cc')
 
 if env['TARGET_ISA'] != 'no':
     SimObject('PhysicalMemory.py')
@@ -58,7 +61,6 @@
     Source('vport.cc')
 elif env['TARGET_ISA'] != 'no':
     Source('page_table.cc')
-    Source('translating_port.cc')
 
 DebugFlag('Bus')
 DebugFlag('BusAddrRanges')
diff -r cca29fccc4b1 -r a976ceb6edd7 src/mem/port_proxy.hh
--- a/src/mem/port_proxy.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/mem/port_proxy.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -51,9 +51,12 @@
 #ifndef __MEM_PORT_PROXY_HH__
 #define __MEM_PORT_PROXY_HH__
 
-#include "arch/isa_traits.hh"
+#include "config/the_isa.hh"
+#if THE_ISA != NO_ISA
+    #include "arch/isa_traits.hh"
+#endif
+
 #include "base/types.hh"
-#include "config/the_isa.hh"
 #include "mem/port.hh"
 #include "sim/byteswap.hh"
 
@@ -112,6 +115,7 @@
     template <typename T>
     void write(Addr address, T data);
 
+#if THE_ISA != NO_ISA
     /**
      * Read sizeof(T) bytes from address and return as object T.
      * Performs Guest to Host endianness transform.
@@ -125,6 +129,7 @@
      */
     template <typename T>
     void writeHtoG(Addr address, T data);
+#endif
 };
 
 
@@ -144,6 +149,7 @@
     _port.writeBlob(address, (uint8_t*)&data, sizeof(T));
 }
 
+#if THE_ISA != NO_ISA
 template <typename T>
 T
 PortProxy::readGtoH(Addr address)
@@ -160,5 +166,6 @@
     data = TheISA::htog(data);
     _port.writeBlob(address, (uint8_t*)&data, sizeof(T));
 }
+#endif
 
 #endif // __MEM_PORT_PROXY_HH__
diff -r cca29fccc4b1 -r a976ceb6edd7 src/mem/se_translating_proxy.hh
--- a/src/mem/se_translating_proxy.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/mem/se_translating_proxy.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -91,7 +91,6 @@
     SETranslatingProxy(Process *p, AllocType a, Port *port);
     virtual ~SETranslatingProxy();
 
-  private:
     // helper functions for read/write/set functions
     bool tryReadMem( Addr address, uint8_t* p, int size);
     bool tryWriteMem(Addr address, uint8_t* p, int size);
diff -r cca29fccc4b1 -r a976ceb6edd7 src/mem/se_translating_proxy.cc
--- a/src/mem/se_translating_proxy.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/mem/se_translating_proxy.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -98,8 +98,8 @@
 
         if (!pTable->translate(gen.addr(), paddr)) {
             if (allocating == Always) {
-                pTable->allocate(roundDown(gen.addr(), VMPageSize),
-                                 VMPageSize);
+                process->allocateMem(roundDown(gen.addr(), VMPageSize),
+                                     VMPageSize);
             } else if (allocating == NextPage) {
                 // check if we've accessed the next page on the stack
                 if (!process->fixupStackFault(gen.addr()))
@@ -127,8 +127,8 @@
 
         if (!pTable->translate(gen.addr(), paddr)) {
             if (allocating == Always) {
-                pTable->allocate(roundDown(gen.addr(), VMPageSize),
-                                 VMPageSize);
+                process->allocateMem(roundDown(gen.addr(), VMPageSize),
+                                     VMPageSize);
                 pTable->translate(gen.addr(), paddr);
             } else {
                 return false;
diff -r cca29fccc4b1 -r a976ceb6edd7 src/python/m5/SimObject.py
--- a/src/python/m5/SimObject.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/python/m5/SimObject.py	Mon Nov 28 18:17:05 2011 +0000
@@ -562,6 +562,7 @@
       Drained
     };
 
+    void setParent(SimObject *p);
     void init();
     void loadState(Checkpoint *cp);
     void initState();
diff -r cca29fccc4b1 -r a976ceb6edd7 src/python/m5/simulate.py
--- a/src/python/m5/simulate.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/python/m5/simulate.py	Mon Nov 28 18:17:05 2011 +0000
@@ -74,8 +74,15 @@
     # Initialize the global statistics
     stats.initSimStats()
 
-    # Create the C++ sim objects and connect ports
+    # Create the C++ sim objects
     for obj in root.descendants(): obj.createCCObject()
+
+    # Set the parent relations
+    for obj in root.descendants():
+        if obj._parent != None:
+            obj.setParent(obj._parent._ccObject)
+
+    # Connect all ports
     for obj in root.descendants(): obj.connectPorts()
 
     # Do a second pass to finish initializing the sim objects
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/System.py
--- a/src/sim/System.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/System.py	Mon Nov 28 18:17:05 2011 +0000
@@ -37,7 +37,7 @@
 
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
 
-class System(SimObject):
+class System(MemObject):
     type = 'System'
 
     @classmethod
@@ -51,6 +51,8 @@
       void setMemoryMode(Enums::MemoryMode mode);
 ''')
 
+    system_port = Port("System Port")
+
     physmem = Param.PhysicalMemory("Physical Memory")
     mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
     memories = VectorParam.PhysicalMemory(Self.all, "All memories is the system")
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/process.hh
--- a/src/sim/process.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/process.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -57,7 +57,7 @@
 class SyscallDesc;
 class System;
 class ThreadContext;
-class TranslatingPort;
+class SETranslatingProxy;
 
 template<class IntType>
 struct AuxVector
@@ -132,7 +132,7 @@
 
   protected:
     /// Memory object for initialization (image loading)
-    TranslatingPort *initVirtMem;
+    SETranslatingProxy *initVirtMem;
 
   public:
     PageTable *pTable;
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/process.cc
--- a/src/sim/process.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/process.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -45,7 +45,7 @@
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "mem/physical.hh"
-#include "mem/translating_port.hh"
+#include "mem/se_translating_proxy.hh"
 #include "params/LiveProcess.hh"
 #include "params/Process.hh"
 #include "sim/debug.hh"
@@ -244,12 +244,8 @@
     // mark this context as active so it will start ticking.
     tc->activate(0);
 
-    Port *mem_port;
-    mem_port = system->physmem->getPort("functional");
-    initVirtMem = new TranslatingPort("process init port", this,
-            TranslatingPort::Always);
-    mem_port->setPeer(initVirtMem);
-    initVirtMem->setPeer(mem_port);
+    initVirtMem = new SETranslatingProxy(this, SETranslatingProxy::Always,
+                                            systemPort());
 }
 
 // map simulator fd sim_fd to target fd tgt_fd
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/process_impl.hh
--- a/src/sim/process_impl.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/process_impl.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -45,10 +45,11 @@
 #include <vector>
 
 #include "mem/translating_port.hh"
+#include "mem/se_translating_proxy.hh"
 #include "sim/byteswap.hh"
 
 //This needs to be templated for cases where 32 bit pointers are needed.
-template<class AddrType>
+/*template<class AddrType>
 void
 copyStringArray(std::vector<std::string> &strings,
         AddrType array_ptr, AddrType data_ptr,
@@ -67,9 +68,30 @@
     data_ptr = 0;
 
     memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(AddrType));
+}*/
+
+//This needs to be templated for cases where 32 bit pointers are needed.
+template<class AddrType>
+void
+copyStringArray(std::vector<std::string> &strings,
+        AddrType array_ptr, AddrType data_ptr,
+        SETranslatingProxy* memProxy)
+{
+    AddrType data_ptr_swap;
+    for (std::vector<std::string>::size_type i = 0; i < strings.size(); ++i) {
+        data_ptr_swap = htog(data_ptr);
+        memProxy->writeMem(array_ptr, (uint8_t*)&data_ptr_swap,
+                sizeof(AddrType));
+        memProxy->writeString(data_ptr, strings[i].c_str());
+        array_ptr += sizeof(AddrType);
+        data_ptr += strings[i].size() + 1;
+    }
+    // add NULL terminator
+    data_ptr = 0;
+
+    memProxy->writeMem(array_ptr, (uint8_t*)&data_ptr, sizeof(AddrType));
 }
 
-
 #endif // !FULL_SYSTEM
 
 #endif
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/sim_object.hh
--- a/src/sim/sim_object.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/sim_object.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -43,6 +43,7 @@
 #include <string>
 #include <vector>
 
+#include "mem/port.hh"
 #include "params/SimObject.hh"
 #include "sim/eventq.hh"
 #include "sim/serialize.hh"
@@ -65,6 +66,16 @@
     };
 
   private:
+    SimObject *_parent;
+
+  public:
+    void setParent(SimObject *p) {
+        _parent = p;
+    }
+
+    virtual Port* systemPort() { return _parent->systemPort(); }
+
+  private:
     State state;
 
   protected:
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/syscall_emul.hh
--- a/src/sim/syscall_emul.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/syscall_emul.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -62,7 +62,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/SyscallVerbose.hh"
 #include "mem/page_table.hh"
-#include "mem/translating_port.hh"
+#include "mem/se_translating_proxy.hh"
 #include "sim/byteswap.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
@@ -120,18 +120,18 @@
     //
     // copy data into simulator space (read from target memory)
     //
-    virtual bool copyIn(TranslatingPort *memport)
+    virtual bool copyIn(SETranslatingProxy *memproxy)
     {
-        memport->readBlob(addr, bufPtr, size);
+        memproxy->readMem(addr, bufPtr, size);
         return true;    // no EFAULT detection for now
     }
 
     //
     // copy data out of simulator space (write to target memory)
     //
-    virtual bool copyOut(TranslatingPort *memport)
+    virtual bool copyOut(SETranslatingProxy *memproxy)
     {
-        memport->writeBlob(addr, bufPtr, size);
+        memproxy->writeMem(addr, bufPtr, size);
         return true;    // no EFAULT detection for now
     }
 
@@ -463,7 +463,7 @@
 //Here are a couple convenience functions
 template<class OS>
 static void
-copyOutStatBuf(TranslatingPort * mem, Addr addr,
+copyOutStatBuf(SETranslatingProxy * mem, Addr addr,
         hst_stat *host, bool fakeTTY = false)
 {
     typedef TypedBufferArg<typename OS::tgt_stat> tgt_stat_buf;
@@ -474,7 +474,7 @@
 
 template<class OS>
 static void
-copyOutStat64Buf(TranslatingPort * mem, Addr addr,
+copyOutStat64Buf(SETranslatingProxy * mem, Addr addr,
         hst_stat64 *host, bool fakeTTY = false)
 {
     typedef TypedBufferArg<typename OS::tgt_stat64> tgt_stat_buf;
@@ -529,7 +529,7 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index)))
         return -EFAULT;
 
@@ -593,7 +593,7 @@
     sysinfo->uptime=seconds_since_epoch;
     sysinfo->totalram=process->system->memSize();
 
-    sysinfo.copyOut(tc->getMemPort());
+    sysinfo.copyOut(tc->getMemProxy());
 
     return 0;
 }
@@ -607,7 +607,7 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index))) {
         return -EFAULT;
     }
@@ -713,7 +713,7 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index))) {
         return -EFAULT;
     }
@@ -728,7 +728,7 @@
     if (result < 0)
         return -errno;
 
-    copyOutStatBuf<OS>(tc->getMemPort(), bufPtr, &hostBuf);
+    copyOutStatBuf<OS>(tc->getMemProxy(), bufPtr, &hostBuf);
 
     return 0;
 }
@@ -743,7 +743,7 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index)))
         return -EFAULT;
     Addr bufPtr = process->getSyscallArg(tc, index);
@@ -762,7 +762,7 @@
     if (result < 0)
         return -errno;
 
-    copyOutStat64Buf<OS>(tc->getMemPort(), bufPtr, &hostBuf);
+    copyOutStat64Buf<OS>(tc->getMemProxy(), bufPtr, &hostBuf);
 
     return 0;
 }
@@ -793,7 +793,7 @@
     if (result < 0)
         return -errno;
 
-    copyOutStat64Buf<OS>(tc->getMemPort(), bufPtr, &hostBuf, (fd == 1));
+    copyOutStat64Buf<OS>(tc->getMemProxy(), bufPtr, &hostBuf, (fd == 1));
 
     return 0;
 }
@@ -808,7 +808,7 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index))) {
         return -EFAULT;
     }
@@ -823,7 +823,7 @@
     if (result < 0)
         return -errno;
 
-    copyOutStatBuf<OS>(tc->getMemPort(), bufPtr, &hostBuf);
+    copyOutStatBuf<OS>(tc->getMemProxy(), bufPtr, &hostBuf);
 
     return 0;
 }
@@ -837,7 +837,7 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index))) {
         return -EFAULT;
     }
@@ -857,7 +857,7 @@
     if (result < 0)
         return -errno;
 
-    copyOutStat64Buf<OS>(tc->getMemPort(), bufPtr, &hostBuf);
+    copyOutStat64Buf<OS>(tc->getMemProxy(), bufPtr, &hostBuf);
 
     return 0;
 }
@@ -883,7 +883,7 @@
     if (result < 0)
         return -errno;
 
-    copyOutStatBuf<OS>(tc->getMemPort(), bufPtr, &hostBuf, (fd == 1));
+    copyOutStatBuf<OS>(tc->getMemProxy(), bufPtr, &hostBuf, (fd == 1));
 
     return 0;
 }
@@ -898,7 +898,7 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index))) {
         return -EFAULT;
     }
@@ -913,7 +913,7 @@
     if (result < 0)
         return -errno;
 
-    OS::copyOutStatfsBuf(tc->getMemPort(), bufPtr, &hostBuf);
+    OS::copyOutStatfsBuf(tc->getMemProxy(), bufPtr, &hostBuf);
 
     return 0;
 }
@@ -938,7 +938,7 @@
     if (result < 0)
         return -errno;
 
-    OS::copyOutStatfsBuf(tc->getMemPort(), bufPtr, &hostBuf);
+    OS::copyOutStatfsBuf(tc->getMemProxy(), bufPtr, &hostBuf);
 
     return 0;
 }
@@ -957,18 +957,18 @@
         return -EBADF;
     }
 
-    TranslatingPort *p = tc->getMemPort();
+    SETranslatingProxy *p = tc->getMemProxy();
     uint64_t tiov_base = process->getSyscallArg(tc, index);
     size_t count = process->getSyscallArg(tc, index);
     struct iovec hiov[count];
     for (size_t i = 0; i < count; ++i) {
         typename OS::tgt_iovec tiov;
 
-        p->readBlob(tiov_base + i*sizeof(typename OS::tgt_iovec),
+        p->readMem(tiov_base + i*sizeof(typename OS::tgt_iovec),
                     (uint8_t*)&tiov, sizeof(typename OS::tgt_iovec));
         hiov[i].iov_len = gtoh(tiov.iov_len);
         hiov[i].iov_base = new char [hiov[i].iov_len];
-        p->readBlob(gtoh(tiov.iov_base), (uint8_t *)hiov[i].iov_base,
+        p->readMem(gtoh(tiov.iov_base), (uint8_t *)hiov[i].iov_base,
                     hiov[i].iov_len);
     }
 
@@ -1102,7 +1102,7 @@
             break;
     }
 
-    rlp.copyOut(tc->getMemPort());
+    rlp.copyOut(tc->getMemProxy());
     return 0;
 }
 
@@ -1120,7 +1120,7 @@
     tp->tv_sec = TheISA::htog(tp->tv_sec);
     tp->tv_usec = TheISA::htog(tp->tv_usec);
 
-    tp.copyOut(tc->getMemPort());
+    tp.copyOut(tc->getMemProxy());
 
     return 0;
 }
@@ -1135,14 +1135,14 @@
     std::string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path,
+    if (!tc->getMemProxy()->tryReadString(path,
                 process->getSyscallArg(tc, index))) {
         return -EFAULT;
     }
 
     TypedBufferArg<typename OS::timeval [2]>
         tp(process->getSyscallArg(tc, index));
-    tp.copyIn(tc->getMemPort());
+    tp.copyIn(tc->getMemProxy());
 
     struct timeval hostTimeval[2];
     for (int i = 0; i < 2; ++i)
@@ -1208,7 +1208,7 @@
              who);
     }
 
-    rup.copyOut(tc->getMemPort());
+    rup.copyOut(tc->getMemProxy());
 
     return 0;
 }
@@ -1233,7 +1233,7 @@
     bufp->tms_utime = htog(bufp->tms_utime);
 
     // Write back
-    bufp.copyOut(tc->getMemPort());
+    bufp.copyOut(tc->getMemProxy());
 
     // Return clock ticks since system boot
     return clocks;
@@ -1254,8 +1254,8 @@
     if(taddr != 0) {
         typename OS::time_t t = sec;
         t = htog(t);
-        TranslatingPort *p = tc->getMemPort();
-        p->writeBlob(taddr, (uint8_t*)&t, (int)sizeof(typename OS::time_t));
+        SETranslatingProxy *p = tc->getMemProxy();
+        p->writeMem(taddr, (uint8_t*)&t, (int)sizeof(typename OS::time_t));
     }
     return sec;
 }
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/syscall_emul.cc
--- a/src/sim/syscall_emul.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/syscall_emul.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -171,18 +171,18 @@
             // if the address is already there, zero it out
             else {
                 uint8_t zero  = 0;
-                TranslatingPort *tp = tc->getMemPort();
+                SETranslatingProxy *tp = tc->getMemProxy();
 
                 // split non-page aligned accesses
                 Addr next_page = roundUp(gen.addr(), VMPageSize);
                 uint32_t size_needed = next_page - gen.addr();
-                tp->memsetBlob(gen.addr(), zero, size_needed);
+                tp->setMem(gen.addr(), zero, size_needed);
                 if (gen.addr() + VMPageSize > next_page &&
                     next_page < new_brk &&
                     p->pTable->translate(next_page))
                 {
                     size_needed = VMPageSize - size_needed;
-                    tp->memsetBlob(next_page, zero, size_needed);
+                    tp->setMem(next_page, zero, size_needed);
                 }
             }
         }
@@ -221,7 +221,7 @@
     int bytes_read = read(fd, bufArg.bufferPtr(), nbytes);
 
     if (bytes_read != -1)
-        bufArg.copyOut(tc->getMemPort());
+        bufArg.copyOut(tc->getMemProxy());
 
     return bytes_read;
 }
@@ -235,7 +235,7 @@
     int nbytes = p->getSyscallArg(tc, index);
     BufferArg bufArg(bufPtr, nbytes);
 
-    bufArg.copyIn(tc->getMemPort());
+    bufArg.copyIn(tc->getMemProxy());
 
     int bytes_written = write(fd, bufArg.bufferPtr(), nbytes);
 
@@ -284,7 +284,7 @@
         // target platform
         BufferArg result_buf(result_ptr, sizeof(result));
         memcpy(result_buf.bufferPtr(), &result, sizeof(result));
-        result_buf.copyOut(tc->getMemPort());
+        result_buf.copyOut(tc->getMemProxy());
         return 0;
     }
 
@@ -313,7 +313,7 @@
 
     strncpy((char *)name.bufferPtr(), hostname, name_len);
 
-    name.copyOut(tc->getMemPort());
+    name.copyOut(tc->getMemProxy());
 
     return 0;
 }
@@ -346,7 +346,7 @@
         }
     }
 
-    buf.copyOut(tc->getMemPort());
+    buf.copyOut(tc->getMemProxy());
 
     return (result == -1) ? -errno : result;
 }
@@ -358,7 +358,7 @@
     string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path, p->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(path, p->getSyscallArg(tc, index)))
         return (TheISA::IntReg)-EFAULT;
 
     // Adjust path for current working directory
@@ -371,7 +371,7 @@
 
     int result = readlink(path.c_str(), (char *)buf.bufferPtr(), bufsiz);
 
-    buf.copyOut(tc->getMemPort());
+    buf.copyOut(tc->getMemProxy());
 
     return (result == -1) ? -errno : result;
 }
@@ -382,7 +382,7 @@
     string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path, p->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(path, p->getSyscallArg(tc, index)))
         return (TheISA::IntReg)-EFAULT;
 
     // Adjust path for current working directory
@@ -399,7 +399,7 @@
     string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path, p->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(path, p->getSyscallArg(tc, index)))
         return (TheISA::IntReg)-EFAULT;
 
     // Adjust path for current working directory
@@ -417,12 +417,12 @@
     string old_name;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(old_name, p->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(old_name, p->getSyscallArg(tc, index)))
         return -EFAULT;
 
     string new_name;
 
-    if (!tc->getMemPort()->tryReadString(new_name, p->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(new_name, p->getSyscallArg(tc, index)))
         return -EFAULT;
 
     // Adjust path for current working directory
@@ -439,7 +439,7 @@
     string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path, p->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(path, p->getSyscallArg(tc, index)))
         return -EFAULT;
 
     off_t length = p->getSyscallArg(tc, index);
@@ -474,7 +474,7 @@
     int index = 0;
     string path;
 
-    if (!tc->getMemPort()->tryReadString(path, process->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(path, process->getSyscallArg(tc, index)))
        return -EFAULT;
 
     int64_t length = process->getSyscallArg(tc, index, 64);
@@ -527,7 +527,7 @@
     string path;
 
     int index = 0;
-    if (!tc->getMemPort()->tryReadString(path, p->getSyscallArg(tc, index)))
+    if (!tc->getMemProxy()->tryReadString(path, p->getSyscallArg(tc, index)))
         return -EFAULT;
 
     /* XXX endianess */
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/system.hh
--- a/src/sim/system.hh	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/system.hh	Mon Nov 28 18:17:05 2011 +0000
@@ -44,9 +44,9 @@
 #include "config/full_system.hh"
 #include "cpu/pc_event.hh"
 #include "enums/MemoryMode.hh"
+#include "mem/mem_object.hh"
 #include "mem/port.hh"
 #include "params/System.hh"
-#include "sim/sim_object.hh"
 
 #if FULL_SYSTEM
 #include "kern/system_events.hh"
@@ -65,8 +65,33 @@
 class GDBListener;
 class BaseRemoteGDB;
 
-class System : public SimObject
+class System : public MemObject
 {
+
+  private:
+    class SystemPort : public Port
+    {
+      public:
+        SystemPort(const std::string &_name, MemObject *_owner)
+        : Port(_name, _owner)
+        { }
+        bool recvTiming(PacketPtr pkt)
+        { panic("SystemPort does not receive anyting!\n"); return false; }
+        Tick recvAtomic(PacketPtr pkt)
+        { panic("SystemPort does not receive anyting!\n"); return 0; }
+        void recvFunctional(PacketPtr pkt)
+        { panic("SystemPort does not receive anyting!\n"); }
+        void recvStatusChange(Status status) { }
+
+    } _systemPort;
+
+  public:
+
+    Port* systemPort() { return &_systemPort; }
+
+    /** Additional function to return the Port of a memory object. */
+    Port *getPort(const std::string &if_name, int idx = -1);
+
   public:
 
     static const char *MemoryModeStrings[3];
diff -r cca29fccc4b1 -r a976ceb6edd7 src/sim/system.cc
--- a/src/sim/system.cc	Mon Nov 28 18:15:15 2011 +0000
+++ b/src/sim/system.cc	Mon Nov 28 18:17:05 2011 +0000
@@ -65,7 +65,10 @@
 int System::numSystemsRunning = 0;
 
 System::System(Params *p)
-    : SimObject(p), physmem(p->physmem), _numContexts(0),
+    : MemObject(p),
+      _systemPort("system_port", this),
+      physmem(p->physmem),
+      _numContexts(0),
 #if FULL_SYSTEM
       init_param(p->init_param),
       loadAddrMask(p->load_addr_mask),
@@ -173,6 +176,12 @@
 #endif // FULL_SYSTEM}
 }
 
+Port*
+System::getPort(const std::string &if_name, int idx)
+{
+    return &_systemPort;
+}
+
 void
 System::setMemoryMode(Enums::MemoryMode mode)
 {
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/inorder-timing.py	Mon Nov 28 18:17:05 2011 +0000
@@ -53,4 +53,6 @@
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
+system.system_port = system.membus.port
+
 root = Root(system = system)
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/memtest.py
--- a/tests/configs/memtest.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/memtest.py	Mon Nov 28 18:17:05 2011 +0000
@@ -79,6 +79,7 @@
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/o3-timing-mp-ruby.py	Mon Nov 28 18:17:05 2011 +0000
@@ -46,6 +46,7 @@
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/o3-timing-mp.py	Mon Nov 28 18:17:05 2011 +0000
@@ -79,6 +79,7 @@
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/o3-timing-ruby.py	Mon Nov 28 18:17:05 2011 +0000
@@ -43,4 +43,6 @@
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
+system.system_port = system.membus.port
+
 root = Root(system = system)
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/o3-timing.py	Mon Nov 28 18:17:05 2011 +0000
@@ -52,4 +52,6 @@
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
+system.system_port = system.membus.port
+
 root = Root(system = system)
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/pc-o3-timing.py	Mon Nov 28 18:17:05 2011 +0000
@@ -110,6 +110,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/pc-simple-atomic.py	Mon Nov 28 18:17:05 2011 +0000
@@ -112,6 +112,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/pc-simple-timing.py	Mon Nov 28 18:17:05 2011 +0000
@@ -112,6 +112,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/realview-o3-dual.py
--- a/tests/configs/realview-o3-dual.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/realview-o3-dual.py	Mon Nov 28 18:17:05 2011 +0000
@@ -96,6 +96,8 @@
     c.clock = '2GHz'
 
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/realview-o3.py	Mon Nov 28 18:17:05 2011 +0000
@@ -94,6 +94,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/realview-simple-atomic-dual.py
--- a/tests/configs/realview-simple-atomic-dual.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/realview-simple-atomic-dual.py	Mon Nov 28 18:17:05 2011 +0000
@@ -96,6 +96,8 @@
     c.clock = '2GHz'
 
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/realview-simple-atomic.py	Mon Nov 28 18:17:05 2011 +0000
@@ -92,6 +92,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/realview-simple-timing-dual.py
--- a/tests/configs/realview-simple-timing-dual.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/realview-simple-timing-dual.py	Mon Nov 28 18:17:05 2011 +0000
@@ -96,6 +96,8 @@
     c.clock = '2GHz'
 
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/realview-simple-timing.py	Mon Nov 28 18:17:05 2011 +0000
@@ -94,6 +94,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/simple-atomic-mp-ruby.py
--- a/tests/configs/simple-atomic-mp-ruby.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/simple-atomic-mp-ruby.py	Mon Nov 28 18:17:05 2011 +0000
@@ -47,6 +47,7 @@
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/simple-atomic-mp.py
--- a/tests/configs/simple-atomic-mp.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/simple-atomic-mp.py	Mon Nov 28 18:17:05 2011 +0000
@@ -78,6 +78,7 @@
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/simple-atomic.py
--- a/tests/configs/simple-atomic.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/simple-atomic.py	Mon Nov 28 18:17:05 2011 +0000
@@ -36,4 +36,6 @@
 system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system = system)
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/simple-timing-mp.py
--- a/tests/configs/simple-timing-mp.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/simple-timing-mp.py	Mon Nov 28 18:17:05 2011 +0000
@@ -78,6 +78,7 @@
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/simple-timing.py
--- a/tests/configs/simple-timing.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/simple-timing.py	Mon Nov 28 18:17:05 2011 +0000
@@ -50,4 +50,6 @@
 cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system = system)
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/t1000-simple-atomic.py
--- a/tests/configs/t1000-simple-atomic.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/t1000-simple-atomic.py	Mon Nov 28 18:17:05 2011 +0000
@@ -36,6 +36,8 @@
 system.cpu = cpu
 cpu.connectAllPorts(system.membus)
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/tsunami-inorder.py
--- a/tests/configs/tsunami-inorder.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/tsunami-inorder.py	Mon Nov 28 18:17:05 2011 +0000
@@ -98,6 +98,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/tsunami-o3-dual.py
--- a/tests/configs/tsunami-o3-dual.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/tsunami-o3-dual.py	Mon Nov 28 18:17:05 2011 +0000
@@ -97,6 +97,8 @@
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/tsunami-o3.py
--- a/tests/configs/tsunami-o3.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/tsunami-o3.py	Mon Nov 28 18:17:05 2011 +0000
@@ -95,6 +95,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/tsunami-simple-atomic-dual.py
--- a/tests/configs/tsunami-simple-atomic-dual.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/tsunami-simple-atomic-dual.py	Mon Nov 28 18:17:05 2011 +0000
@@ -95,5 +95,7 @@
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/tsunami-simple-atomic.py
--- a/tests/configs/tsunami-simple-atomic.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/tsunami-simple-atomic.py	Mon Nov 28 18:17:05 2011 +0000
@@ -93,6 +93,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/tsunami-simple-timing-dual.py
--- a/tests/configs/tsunami-simple-timing-dual.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/tsunami-simple-timing-dual.py	Mon Nov 28 18:17:05 2011 +0000
@@ -95,6 +95,8 @@
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/tsunami-simple-timing.py
--- a/tests/configs/tsunami-simple-timing.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/tsunami-simple-timing.py	Mon Nov 28 18:17:05 2011 +0000
@@ -95,6 +95,8 @@
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
+system.system_port = system.membus.port
+
 root = Root(system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff -r cca29fccc4b1 -r a976ceb6edd7 tests/configs/twosys-tsunami-simple-atomic.py
--- a/tests/configs/twosys-tsunami-simple-atomic.py	Mon Nov 28 18:15:15 2011 +0000
+++ b/tests/configs/twosys-tsunami-simple-atomic.py	Mon Nov 28 18:17:05 2011 +0000
@@ -36,11 +36,15 @@
                                  SysConfig('netperf-stream-client.rcS'))
 test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
 test_sys.cpu.connectAllPorts(test_sys.membus)
+test_sys.system_port = test_sys.membus.port
+
 
 drive_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-server.rcS'))
 drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
 drive_sys.cpu.connectAllPorts(drive_sys.membus)
+drive_sys.system_port = drive_sys.membus.port
+
 
 root = makeDualRoot(test_sys, drive_sys, "ethertrace")