diff -r a976ceb6edd7 -r a9dea608f34e configs/ruby/Ruby.py --- a/configs/ruby/Ruby.py Mon Nov 28 18:17:05 2011 +0000 +++ b/configs/ruby/Ruby.py Mon Nov 28 18:19:26 2011 +0000 @@ -78,6 +78,17 @@ print "Error: could not create sytem for ruby protocol %s" % protocol raise + # Create a system sequencer for connecting the system port. This + # is independent of the protocol and kept in the protocol-agnostic + # part (i.e. here). + sys_sequencer = SystemSequencer(version = 0, + physMemPort = system.physmem.port, + physmem = system.physmem, + ruby_system = ruby) + # Give the system sequencer a SimObject parent without creating a + # full-fledged controller + system.sys_sequencer = sys_sequencer + # # Set the network classes based on the command line options # @@ -158,4 +169,5 @@ ruby.tracer = ruby_tracer ruby.mem_size = total_mem_size ruby._cpu_ruby_ports = cpu_sequencers + ruby._sys_ruby_port = sys_sequencer ruby.random_seed = options.random_seed diff -r a976ceb6edd7 -r a9dea608f34e src/mem/ruby/SConscript --- a/src/mem/ruby/SConscript Mon Nov 28 18:17:05 2011 +0000 +++ b/src/mem/ruby/SConscript Mon Nov 28 18:19:26 2011 +0000 @@ -105,6 +105,7 @@ MakeInclude('filters/GenericBloomFilter.hh') MakeInclude('system/CacheMemory.hh') MakeInclude('system/DMASequencer.hh') +MakeInclude('system/SystemSequencer.hh') MakeInclude('system/DirectoryMemory.hh') MakeInclude('system/MachineID.hh') MakeInclude('system/MemoryControl.hh') diff -r a976ceb6edd7 -r a9dea608f34e src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc Mon Nov 28 18:17:05 2011 +0000 +++ b/src/mem/ruby/system/RubyPort.cc Mon Nov 28 18:19:26 2011 +0000 @@ -460,8 +460,10 @@ // turn packet around to go back to requester if response expected if (needsResponse) { pkt->setFunctionalResponseStatus(accessSucceeded); - DPRINTF(RubyPort, "Sending packet back over port\n"); - sendFunctional(pkt); + + // @todo Surely there should not be a reverse call + // DPRINTF(RubyPort, "Sending packet back over port\n"); + // sendFunctional(pkt); } DPRINTF(RubyPort, "Functional access %s!\n", accessSucceeded ? "successful":"failed"); diff -r a976ceb6edd7 -r a9dea608f34e src/mem/ruby/system/SConscript --- a/src/mem/ruby/system/SConscript Mon Nov 28 18:17:05 2011 +0000 +++ b/src/mem/ruby/system/SConscript Mon Nov 28 18:19:26 2011 +0000 @@ -41,6 +41,7 @@ SimObject('RubySystem.py') Source('DMASequencer.cc') +Source('SystemSequencer.cc') Source('DirectoryMemory.cc') Source('SparseMemory.cc') Source('CacheMemory.cc') diff -r a976ceb6edd7 -r a9dea608f34e src/mem/ruby/system/Sequencer.py --- a/src/mem/ruby/system/Sequencer.py Mon Nov 28 18:17:05 2011 +0000 +++ b/src/mem/ruby/system/Sequencer.py Mon Nov 28 18:19:26 2011 +0000 @@ -57,3 +57,6 @@ class DMASequencer(RubyPort): type = 'DMASequencer' + +class SystemSequencer(RubyPort): + type = 'SystemSequencer' diff -r a976ceb6edd7 -r a9dea608f34e src/mem/ruby/system/SystemSequencer.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/mem/ruby/system/SystemSequencer.hh Mon Nov 28 18:19:26 2011 +0000 @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +/** + * @file + * SystemSequencer for connecting system port to Ruby + * + * A trivial sequencer that allows the system port to connect to Ruby + * and use nothing but functional accesses. + */ + +#ifndef __MEM_RUBY_SYSTEM_SYSTEMSEQUENCER_HH__ +#define __MEM_RUBY_SYSTEM_SYSTEMSEQUENCER_HH__ + +#include "mem/ruby/system/RubyPort.hh" +#include "params/SystemSequencer.hh" + +class SystemSequencer : public RubyPort +{ + + public: + + /** + * Create a new SystemSequencer. + * + * @param p Parameters inherited from the RubyPort + */ + SystemSequencer(const SystemSequencerParams* p); + + /** + * Destruct a SystemSequencer. + */ + virtual ~SystemSequencer(); + + /** + * Initialise a SystemSequencer by doing nothing and avoid + * involving the super class. + */ + void init(); + + /** + * Abstract member in the super class that we are forced to + * implement even if it is never used (since there are only + * functional accesses). + * + * @param pkt The packet to serve to Ruby + */ + RequestStatus makeRequest(PacketPtr pkt); + +}; + +#endif // __MEM_RUBY_SYSTEM_SYSTEMSEQUENCER_HH__ diff -r a976ceb6edd7 -r a9dea608f34e src/mem/ruby/system/SystemSequencer.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/mem/ruby/system/SystemSequencer.cc Mon Nov 28 18:19:26 2011 +0000 @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +#include "mem/ruby/system/SystemSequencer.hh" + +SystemSequencer::SystemSequencer(const SystemSequencerParams* p) : + RubyPort(p) { +} + +SystemSequencer::~SystemSequencer() +{ +} + +void +SystemSequencer::init() +{ + // Merely override to not care about the m_controller being NULL +} + +RequestStatus +SystemSequencer::makeRequest(PacketPtr pkt) +{ + // This sequencer should only be used through the functional + // accesses made by the system port and so simply fail if this + // happens. + panic("SystemSequencer::makeRequest should not be called"); + return RequestStatus_NULL; +} + +SystemSequencer* +SystemSequencerParams::create() +{ + return new SystemSequencer(this); +} diff -r a976ceb6edd7 -r a9dea608f34e src/sim/system.hh --- a/src/sim/system.hh Mon Nov 28 18:17:05 2011 +0000 +++ b/src/sim/system.hh Mon Nov 28 18:19:26 2011 +0000 @@ -76,11 +76,11 @@ : Port(_name, _owner) { } bool recvTiming(PacketPtr pkt) - { panic("SystemPort does not receive anyting!\n"); return false; } + { panic("SystemPort does not receive timing!\n"); return false; } Tick recvAtomic(PacketPtr pkt) - { panic("SystemPort does not receive anyting!\n"); return 0; } + { panic("SystemPort does not receive atomic!\n"); return 0; } void recvFunctional(PacketPtr pkt) - { panic("SystemPort does not receive anyting!\n"); } + { panic("SystemPort does not receive functional!\n"); } void recvStatusChange(Status status) { } } _systemPort; diff -r a976ceb6edd7 -r a9dea608f34e tests/configs/simple-timing-mp-ruby.py --- a/tests/configs/simple-timing-mp-ruby.py Mon Nov 28 18:17:05 2011 +0000 +++ b/tests/configs/simple-timing-mp-ruby.py Mon Nov 28 18:19:26 2011 +0000 @@ -88,6 +88,9 @@ cpu.icache_port = system.ruby._cpu_ruby_ports[i].port cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_ruby_port.port + # ----------------------- # run simulation # ----------------------- diff -r a976ceb6edd7 -r a9dea608f34e tests/configs/simple-timing-ruby.py --- a/tests/configs/simple-timing-ruby.py Mon Nov 28 18:17:05 2011 +0000 +++ b/tests/configs/simple-timing-ruby.py Mon Nov 28 18:19:26 2011 +0000 @@ -85,6 +85,9 @@ cpu.icache_port = system.ruby._cpu_ruby_ports[0].port cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port +# Connect the system port for loading of binaries etc +system.system_port = system.ruby._sys_ruby_port.port + # ----------------------- # run simulation # -----------------------