diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/freebsd/system.cc
--- a/src/arch/alpha/freebsd/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/freebsd/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -78,8 +78,8 @@
     ppc_vaddr = (Addr)tc->readIntReg(17);
     timer_vaddr = (Addr)tc->readIntReg(18);
 
-    virtPort->write(ppc_vaddr, (uint32_t)SimClock::Frequency);
-    virtPort->write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
+    translatingProxy->write(ppc_vaddr, (uint32_t)SimClock::Frequency);
+    translatingProxy->write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
 }
 
 void
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/linux/system.cc
--- a/src/arch/alpha/linux/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/linux/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -85,7 +85,7 @@
      * Since we aren't using a bootloader, we have to copy the
      * kernel arguments directly into the kernel's memory.
      */
-    virtPort->writeMem(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
+    translatingProxy->writeMem(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
                 params()->boot_osflags.length()+1);
 
     /**
@@ -94,7 +94,7 @@
      * calculated it by using the PIT, RTC, etc.
      */
     if (kernelSymtab->findAddress("est_cycle_freq", addr))
-        virtPort->write(addr, (uint64_t)(SimClock::Frequency /
+        translatingProxy->write(addr, (uint64_t)(SimClock::Frequency /
                     params()->boot_cpu_frequency));
 
 
@@ -105,7 +105,7 @@
      * 255 ASNs.
      */
     if (kernelSymtab->findAddress("dp264_mv", addr))
-        virtPort->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+        translatingProxy->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
     else
         panic("could not find dp264_mv\n");
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/linux/threadinfo.hh
--- a/src/arch/alpha/linux/threadinfo.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/linux/threadinfo.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -78,8 +78,8 @@
         if (!addr)
             addr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23);
 
-        FunctionalPort *p = tc->getPhysPort();
-        p->readBlob(addr, (uint8_t *)&sp, sizeof(Addr));
+        PortProxy *p = tc->getPortProxy();
+        p->readMem(addr, (uint8_t *)&sp, sizeof(Addr));
 
         return sp & ~ULL(0x3fff);
     }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/remote_gdb.cc
--- a/src/arch/alpha/remote_gdb.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/remote_gdb.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -192,7 +192,7 @@
 
         Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
         PageTableEntry pte =
-            kernel_pte_lookup(context->getPhysPort(), ptbr, va);
+            kernel_pte_lookup(context->getPortProxy(), ptbr, va);
         if (!pte.valid()) {
             DPRINTF(GDBAcc, "acc:   %#x pte is invalid\n", va);
             return false;
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/system.cc
--- a/src/arch/alpha/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -83,8 +83,8 @@
     System::initState();
 
     // Load program sections into memory
-    pal->loadSections(functionalPort, loadAddrMask);
-    console->loadSections(functionalPort, loadAddrMask);
+    pal->loadSections(initProxy, loadAddrMask);
+    console->loadSections(initProxy, loadAddrMask);
 
     // load symbols
     if (!console->loadGlobalSymbols(consoleSymtab))
@@ -178,8 +178,8 @@
     // lda  gp,Y(gp): opcode 8, Ra = 29, rb = 29
     const uint32_t gp_lda_pattern  = (8 << 26) | (29 << 21) | (29 << 16);
 
-    uint32_t i1 = virtPort->read<uint32_t>(addr);
-    uint32_t i2 = virtPort->read<uint32_t>(addr + sizeof(MachInst));
+    uint32_t i1 = translatingProxy->read<uint32_t>(addr);
+    uint32_t i2 = translatingProxy->read<uint32_t>(addr + sizeof(MachInst));
 
     if ((i1 & inst_mask) == gp_ldah_pattern &&
         (i2 & inst_mask) == gp_lda_pattern) {
@@ -196,7 +196,7 @@
 {
     Addr addr = 0;
     if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
-        virtPort->write(addr, htog(Phys2K0Seg(access)));
+        translatingProxy->write(addr, htog(Phys2K0Seg(access)));
     } else {
         panic("could not find m5AlphaAccess\n");
     }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/tru64/system.cc
--- a/src/arch/alpha/tru64/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/tru64/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -49,7 +49,7 @@
 {
     Addr addr = 0;
     if (kernelSymtab->findAddress("enable_async_printf", addr)) {
-        virtPort->write(addr, (uint32_t)0);
+        translatingProxy->write(addr, (uint32_t)0);
     }
 
 #ifdef DEBUG
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/vtophys.hh
--- a/src/arch/alpha/vtophys.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/vtophys.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -37,11 +37,11 @@
 #include "arch/alpha/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
+class PortProxy;
 
 namespace AlphaISA {
 
-PageTableEntry kernel_pte_lookup(FunctionalPort *mem, Addr ptbr,
+PageTableEntry kernel_pte_lookup(PortProxy *mem, Addr ptbr,
                                  VAddr vaddr);
 
 Addr vtophys(Addr vaddr);
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/alpha/vtophys.cc
--- a/src/arch/alpha/vtophys.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/alpha/vtophys.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -38,14 +38,14 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "debug/VtoPhys.hh"
-#include "mem/port.hh"
+#include "mem/port_proxy.hh"
 
 using namespace std;
 
 namespace AlphaISA {
 
 PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr)
+kernel_pte_lookup(PortProxy *mem, Addr ptbr, VAddr vaddr)
 {
     Addr level1_pte = ptbr + vaddr.level1();
     PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
@@ -103,7 +103,7 @@
             paddr = vaddr;
         } else {
             PageTableEntry pte =
-                kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
+                kernel_pte_lookup(tc->getPortProxy(), ptbr, vaddr);
             if (pte.valid())
                 paddr = pte.paddr() | vaddr.offset();
         }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/arm/linux/system.cc
--- a/src/arch/arm/linux/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/arm/linux/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -50,6 +50,7 @@
 #include "debug/Loader.hh"
 #include "kern/linux/events.hh"
 #include "mem/physical.hh"
+#include "mem/port_proxy.hh"
 
 using namespace ArmISA;
 using namespace Linux;
@@ -99,7 +100,7 @@
     DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
     DDUMP(Loader, boot_data, size << 2);
 
-    functionalPort->writeBlob(ParamsList, boot_data, size << 2);
+    initProxy->writeMem(ParamsList, boot_data, size << 2);
 
 #ifndef NDEBUG
     kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic");
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/arm/process.cc
--- a/src/arch/arm/process.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/arm/process.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -50,7 +50,6 @@
 #include "cpu/thread_context.hh"
 #include "debug/Stack.hh"
 #include "mem/page_table.hh"
-#include "mem/translating_port.hh"
 #include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/arm/system.cc
--- a/src/arch/arm/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/arm/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -47,6 +47,7 @@
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
 #include "mem/physical.hh"
+#include "mem/port_proxy.hh"
 
 using namespace std;
 using namespace Linux;
@@ -71,11 +72,11 @@
         if (!bootldr)
             fatal("Could not read bootloader: %s\n", params()->boot_loader);
 
-        Port *mem_port;
-        FunctionalPort fp(name() + "-fport");
-        mem_port = params()->boot_loader_mem->getPort("functional");
-        fp.setPeer(mem_port);
-        mem_port->setPeer(&fp);
+        // Ideally fp should use the systemPort() here, but the address mapping
+        // of the IO cache prevents the iobus from realizing that it should
+        // not forward the request to the default slave.
+        Port *boot_loader_port = params()->boot_loader_mem->getPort("port",0);
+        PortProxy fp(boot_loader_port->getPeer());
 
         bootldr->loadSections(&fp);
         bootldr->loadGlobalSymbols(debugSymbolTable);
@@ -84,7 +85,7 @@
         {
             0x07, 0xf0, 0xa0, 0xe1  // branch to r7
         };
-        functionalPort->writeBlob(0x0, jump_to_bl, sizeof(jump_to_bl));
+        initProxy->writeMem(0x0, jump_to_bl, sizeof(jump_to_bl));
 
         inform("Using bootloader at address %#x\n", bootldr->entryPoint());
     }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/arm/vtophys.hh
--- a/src/arch/arm/vtophys.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/arm/vtophys.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -38,7 +38,7 @@
 #include "arch/arm/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
+class PortProxy;
 
 namespace ArmISA {
     inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/arm/vtophys.cc
--- a/src/arch/arm/vtophys.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/arm/vtophys.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -51,7 +51,7 @@
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "mem/port.hh"
+#include "mem/port_proxy.hh"
 
 using namespace std;
 using namespace ArmISA;
@@ -101,7 +101,7 @@
         N = 0;
     }
 
-    FunctionalPort *port = tc->getPhysPort();
+    PortProxy *port = tc->getPortProxy();
     Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(addr,31-N,20) << 2);
 
     TableWalker::L1Descriptor l1desc;
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/mips/linux/system.cc
--- a/src/arch/mips/linux/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/mips/linux/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -76,7 +76,7 @@
      * Since we aren't using a bootloader, we have to copy the
      * kernel arguments directly into the kernel's memory.
      */
-    virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
+    translatingProxy.writeMem(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
                 params()->boot_osflags.length()+1);
 
     /**
@@ -85,7 +85,7 @@
      * calculated it by using the PIT, RTC, etc.
      */
     if (kernelSymtab->findAddress("est_cycle_freq", addr))
-        virtPort.write(addr, (uint64_t)(SimClock::Frequency /
+        translatingProxy.write(addr, (uint64_t)(SimClock::Frequency /
                     p->boot_cpu_frequency));
 
     /**
@@ -95,7 +95,7 @@
      * 255 ASNs.
      */
     if (kernelSymtab->findAddress("dp264_mv", addr))
-        virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+        translatingProxy.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
     else
         panic("could not find dp264_mv\n");
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/mips/linux/threadinfo.hh
--- a/src/arch/mips/linux/threadinfo.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/mips/linux/threadinfo.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -79,8 +79,8 @@
         if (!addr)
             addr = tc->readMiscRegNoEffect(0/*MipsISA::IPR_PALtemp23*/);
 
-        FunctionalPort *p = tc->getPhysPort();
-        p->readBlob(addr, (uint8_t *)&sp, sizeof(Addr));
+        PortProxy *p = tc->getPortProxy();
+        p->readMem(addr, (uint8_t *)&sp, sizeof(Addr));
 
         return sp & ~ULL(0x3fff);
     }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/mips/system.cc
--- a/src/arch/mips/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/mips/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -49,7 +49,7 @@
 #if FULL_SYSTEM
     if (p->bare_iron == true) {
         hexFile = new HexFile(params()->hex_file_name);
-        if (!hexFile->loadSections(functionalPort))
+        if (!hexFile->loadSections(initProxy))
             panic("Could not load hex file\n");
     }
 
@@ -69,7 +69,7 @@
     if (console == NULL)
         fatal("Could not load console file %s", params()->console);
     //Load program sections into memory
-    console->loadSections(functionalPort, loadAddrMask);
+    console->loadSections(initProxy, loadAddrMask);
 
     //load symbols
     if (!console->loadGlobalSymbols(consoleSymtab))
@@ -91,7 +91,7 @@
      */
     if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
         warn("writing addr starting from %#x", addr);
-        virtPort->writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
+        translatingProxy->writeMem(addr, (uint8_t*)params()->boot_osflags.c_str(),
                 strlen(params()->boot_osflags.c_str()));
     }
 
@@ -102,9 +102,9 @@
     if (consoleSymtab->findAddress("m5_rpb", addr)) {
         uint64_t data;
         data = htog(params()->system_type);
-        virtPort->write(addr + 0x50, data);
+        translatingProxy->write(addr + 0x50, data);
         data = htog(params()->system_rev);
-        virtPort->write(addr + 0x58, data);
+        translatingProxy->write(addr + 0x58, data);
     } else {
         panic("could not find hwrpb\n");
     }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/mips/vtophys.hh
--- a/src/arch/mips/vtophys.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/mips/vtophys.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -38,7 +38,7 @@
 #include "arch/mips/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
+class PortProxy;
 
 namespace MipsISA {
     inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/power/process.cc
--- a/src/arch/power/process.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/power/process.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -39,7 +39,6 @@
 #include "cpu/thread_context.hh"
 #include "debug/Stack.hh"
 #include "mem/page_table.hh"
-#include "mem/translating_port.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/power/vtophys.hh
--- a/src/arch/power/vtophys.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/power/vtophys.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -40,7 +40,7 @@
 #include "arch/power/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
+class PortProxy;
 
 namespace PowerISA {
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/sparc/process.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -41,7 +41,6 @@
 #include "cpu/thread_context.hh"
 #include "debug/Stack.hh"
 #include "mem/page_table.hh"
-#include "mem/translating_port.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/sparc/system.hh
--- a/src/arch/sparc/system.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/sparc/system.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -37,6 +37,7 @@
 #include "base/loader/symtab.hh"
 #include "cpu/pc_event.hh"
 #include "kern/system_events.hh"
+#include "mem/port_proxy.hh"
 #include "params/SparcSystem.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
@@ -97,16 +98,16 @@
     Tick sysTick;
 
     /** functional port to ROM */
-    FunctionalPort funcRomPort;
+    PortProxy funcRomPort;
 
     /** functional port to nvram */
-    FunctionalPort funcNvramPort;
+    PortProxy funcNvramPort;
 
     /** functional port to hypervisor description */
-    FunctionalPort funcHypDescPort;
+    PortProxy funcHypDescPort;
 
     /** functional port to partition description */
-    FunctionalPort funcPartDescPort;
+    PortProxy funcPartDescPort;
 
   protected:
     const Params *params() const { return (const Params *)_params; }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/sparc/system.cc
--- a/src/arch/sparc/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/sparc/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -40,10 +40,11 @@
 using namespace BigEndianGuest;
 
 SparcSystem::SparcSystem(Params *p)
-    : System(p), sysTick(0),funcRomPort(p->name + "-fromport"),
-    funcNvramPort(p->name + "-fnvramport"),
-    funcHypDescPort(p->name + "-fhypdescport"),
-    funcPartDescPort(p->name + "-fpartdescport")
+    : System(p), sysTick(0),
+    funcRomPort(params()->rom->getPort("port",0)->getPeer()),
+    funcNvramPort(params()->nvram->getPort("port",0)->getPeer()),
+    funcHypDescPort(params()->hypervisor_desc->getPort("port",0)->getPeer()),
+    funcPartDescPort(params()->partition_desc->getPort("port",0)->getPeer())
 {
     resetSymtab = new SymbolTable;
     hypervisorSymtab = new SymbolTable;
@@ -51,23 +52,6 @@
     nvramSymtab = new SymbolTable;
     hypervisorDescSymtab = new SymbolTable;
     partitionDescSymtab = new SymbolTable;
-
-    Port *rom_port;
-    rom_port = params()->rom->getPort("functional");
-    funcRomPort.setPeer(rom_port);
-    rom_port->setPeer(&funcRomPort);
-
-    rom_port = params()->nvram->getPort("functional");
-    funcNvramPort.setPeer(rom_port);
-    rom_port->setPeer(&funcNvramPort);
-
-    rom_port = params()->hypervisor_desc->getPort("functional");
-    funcHypDescPort.setPeer(rom_port);
-    rom_port->setPeer(&funcHypDescPort);
-
-    rom_port = params()->partition_desc->getPort("functional");
-    funcPartDescPort.setPeer(rom_port);
-    rom_port->setPeer(&funcPartDescPort);
 }
 
 void
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/sparc/vtophys.hh
--- a/src/arch/sparc/vtophys.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/sparc/vtophys.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -36,12 +36,12 @@
 #include "arch/sparc/pagetable.hh"
 
 class ThreadContext;
-class FunctionalPort;
+class PortProxy;
 
 namespace SparcISA {
 
 PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
+kernel_pte_lookup(PortProxy *mem, Addr ptbr, SparcISA::VAddr vaddr);
 
 Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/sparc/vtophys.cc
--- a/src/arch/sparc/vtophys.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/sparc/vtophys.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -37,7 +37,7 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "debug/VtoPhys.hh"
-#include "mem/port.hh"
+#include "mem/port_proxy.hh"
 #include "sim/byteswap.hh"
 
 using namespace std;
@@ -82,7 +82,7 @@
     int pri_context = bits(tlbdata,47,32);
     // int sec_context = bits(tlbdata,63,48);
 
-    FunctionalPort *mem = tc->getPhysPort();
+    PortProxy *mem = tc->getPortProxy();
     TLB* itb = tc->getITBPtr();
     TLB* dtb = tc->getDTBPtr();
     TlbEntry* tbe;
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/bios/e820.hh
--- a/src/arch/x86/bios/e820.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/bios/e820.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -47,7 +47,7 @@
 #include "params/X86E820Table.hh"
 #include "sim/sim_object.hh"
 
-class Port;
+class PortProxy;
 
 namespace X86ISA
 {
@@ -75,7 +75,7 @@
         E820Table(Params *p) : SimObject(p), entries(p->entries)
         {}
 
-        void writeTo(Port * port, Addr countAddr, Addr addr);
+        void writeTo(PortProxy * port, Addr countAddr, Addr addr);
     };
 };
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/bios/e820.cc
--- a/src/arch/x86/bios/e820.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/bios/e820.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -39,21 +39,21 @@
 
 #include "arch/x86/bios/e820.hh"
 #include "arch/x86/isa_traits.hh"
-#include "mem/port.hh"
+#include "mem/port_proxy.hh"
 #include "sim/byteswap.hh"
 
 using namespace std;
 using namespace X86ISA;
 
 template<class T>
-void writeVal(T val, Port * port, Addr &addr)
+void writeVal(T val, PortProxy * port, Addr &addr)
 {
     T guestVal = htog(val);
-    port->writeBlob(addr, (uint8_t *)&guestVal, sizeof(T));
+    port->writeMem(addr, (uint8_t *)&guestVal, sizeof(T));
     addr += sizeof(T);
 }
 
-void X86ISA::E820Table::writeTo(Port * port, Addr countAddr, Addr addr)
+void X86ISA::E820Table::writeTo(PortProxy * port, Addr countAddr, Addr addr)
 {
     uint8_t e820Nr = entries.size();
 
@@ -63,7 +63,7 @@
 
     uint8_t guestE820Nr = htog(e820Nr);
 
-    port->writeBlob(countAddr, (uint8_t *)&guestE820Nr, sizeof(guestE820Nr));
+    port->writeMem(countAddr, (uint8_t *)&guestE820Nr, sizeof(guestE820Nr));
 
     for (int i = 0; i < e820Nr; i++) {
         writeVal(entries[i]->addr, port, addr);
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/bios/intelmp.hh
--- a/src/arch/x86/bios/intelmp.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/bios/intelmp.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -51,7 +51,7 @@
 #include "enums/X86IntelMPTriggerMode.hh"
 #include "sim/sim_object.hh"
 
-class FunctionalPort;
+class PortProxy;
 
 // Config entry types
 class X86IntelMPBaseConfigEntryParams;
@@ -93,7 +93,7 @@
 
   public:
 
-    Addr writeOut(FunctionalPort * port, Addr addr);
+    Addr writeOut(PortProxy * port, Addr addr);
 
     Addr getTableAddr()
     {
@@ -117,7 +117,7 @@
 
   public:
 
-    virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    virtual Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     BaseConfigEntry(Params * p, uint8_t _type);
 };
@@ -132,7 +132,7 @@
 
   public:
 
-    virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    virtual Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length);
 };
@@ -155,7 +155,7 @@
     std::vector<ExtConfigEntry *> extEntries;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr);
+    Addr writeOut(PortProxy * port, Addr addr);
 
     ConfigTable(Params * p);
 };
@@ -172,7 +172,7 @@
     uint32_t featureFlags;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     Processor(Params * p);
 };
@@ -186,7 +186,7 @@
     std::string busType;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     Bus(Params * p);
 };
@@ -202,7 +202,7 @@
     uint32_t address;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     IOAPIC(Params * p);
 };
@@ -221,7 +221,7 @@
     uint8_t destApicIntIn;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     IntAssignment(X86IntelMPBaseConfigEntryParams * p,
             Enums::X86IntelMPInterruptType _interruptType,
@@ -269,7 +269,7 @@
     uint64_t addrLength;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     AddrSpaceMapping(Params * p);
 };
@@ -284,7 +284,7 @@
     uint8_t parentBus;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     BusHierarchy(Params * p);
 };
@@ -299,7 +299,7 @@
     uint32_t rangeList;
 
   public:
-    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
+    Addr writeOut(PortProxy * port, Addr addr, uint8_t &checkSum);
 
     CompatAddrSpaceMod(Params * p);
 };
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/bios/intelmp.cc
--- a/src/arch/x86/bios/intelmp.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/bios/intelmp.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -41,7 +41,7 @@
 #include "arch/x86/isa_traits.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
-#include "mem/port.hh"
+#include "mem/port_proxy.hh"
 #include "sim/byteswap.hh"
 
 // Config entry types
@@ -70,10 +70,10 @@
 
 template<class T>
 uint8_t
-writeOutField(FunctionalPort * port, Addr addr, T val)
+writeOutField(PortProxy * port, Addr addr, T val)
 {
     T guestVal = X86ISA::htog(val);
-    port->writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T));
+    port->writeMem(addr, (uint8_t *)(&guestVal), sizeof(T));
 
     uint8_t checkSum = 0;
     while(guestVal) {
@@ -84,7 +84,7 @@
 }
 
 uint8_t
-writeOutString(FunctionalPort * port, Addr addr, string str, int length)
+writeOutString(PortProxy * port, Addr addr, string str, int length)
 {
     char cleanedString[length + 1];
     cleanedString[length] = 0;
@@ -97,7 +97,7 @@
         memcpy(cleanedString, str.c_str(), str.length());
         memset(cleanedString + str.length(), 0, length - str.length());
     }
-    port->writeBlob(addr, (uint8_t *)(&cleanedString), length);
+    port->writeMem(addr, (uint8_t *)(&cleanedString), length);
 
     uint8_t checkSum = 0;
     for (int i = 0; i < length; i++)
@@ -107,7 +107,7 @@
 }
 
 Addr
-X86ISA::IntelMP::FloatingPointer::writeOut(FunctionalPort * port, Addr addr)
+X86ISA::IntelMP::FloatingPointer::writeOut(PortProxy * port, Addr addr)
 {
     // Make sure that either a config table is present or a default
     // configuration was found but not both.
@@ -120,7 +120,7 @@
 
     uint8_t checkSum = 0;
 
-    port->writeBlob(addr, (uint8_t *)signature, 4);
+    port->writeMem(addr, (uint8_t *)signature, 4);
     for (int i = 0; i < 4; i++)
         checkSum += signature[i];
 
@@ -128,20 +128,20 @@
 
     // The length of the structure in paragraphs, aka 16 byte chunks.
     uint8_t length = 1;
-    port->writeBlob(addr + 8, &length, 1);
+    port->writeMem(addr + 8, &length, 1);
     checkSum += length;
 
-    port->writeBlob(addr + 9, &specRev, 1);
+    port->writeMem(addr + 9, &specRev, 1);
     checkSum += specRev;
 
-    port->writeBlob(addr + 11, &defaultConfig, 1);
+    port->writeMem(addr + 11, &defaultConfig, 1);
     checkSum += defaultConfig;
 
     uint32_t features2_5 = imcrPresent ? (1 << 7) : 0;
     checkSum += writeOutField(port, addr + 12, features2_5);
 
     checkSum = -checkSum;
-    port->writeBlob(addr + 10, &checkSum, 1);
+    port->writeMem(addr + 10, &checkSum, 1);
 
     return 16;
 }
@@ -158,10 +158,10 @@
 }
 
 Addr
-X86ISA::IntelMP::BaseConfigEntry::writeOut(FunctionalPort * port,
+X86ISA::IntelMP::BaseConfigEntry::writeOut(PortProxy * port,
         Addr addr, uint8_t &checkSum)
 {
-    port->writeBlob(addr, &type, 1);
+    port->writeMem(addr, &type, 1);
     checkSum += type;
     return 1;
 }
@@ -171,12 +171,12 @@
 {}
 
 Addr
-X86ISA::IntelMP::ExtConfigEntry::writeOut(FunctionalPort * port,
+X86ISA::IntelMP::ExtConfigEntry::writeOut(PortProxy * port,
         Addr addr, uint8_t &checkSum)
 {
-    port->writeBlob(addr, &type, 1);
+    port->writeMem(addr, &type, 1);
     checkSum += type;
-    port->writeBlob(addr + 1, &length, 1);
+    port->writeMem(addr + 1, &length, 1);
     checkSum += length;
     return 1;
 }
@@ -189,17 +189,17 @@
 const char X86ISA::IntelMP::ConfigTable::signature[] = "PCMP";
 
 Addr
-X86ISA::IntelMP::ConfigTable::writeOut(FunctionalPort * port, Addr addr)
+X86ISA::IntelMP::ConfigTable::writeOut(PortProxy * port, Addr addr)
 {
     uint8_t checkSum = 0;
 
-    port->writeBlob(addr, (uint8_t *)signature, 4);
+    port->writeMem(addr, (uint8_t *)signature, 4);
     for (int i = 0; i < 4; i++)
         checkSum += signature[i];
 
     // Base table length goes here but will be calculated later.
 
-    port->writeBlob(addr + 6, (uint8_t *)(&specRev), 1);
+    port->writeMem(addr + 6, (uint8_t *)(&specRev), 1);
     checkSum += specRev;
 
     // The checksum goes here but is still being calculated.
@@ -213,7 +213,7 @@
     checkSum += writeOutField(port, addr + 36, localApic);
 
     uint8_t reserved = 0;
-    port->writeBlob(addr + 43, &reserved, 1);
+    port->writeMem(addr + 43, &reserved, 1);
     checkSum += reserved;
 
     vector<BaseConfigEntry *>::iterator baseEnt;
@@ -261,7 +261,7 @@
 
 Addr
 X86ISA::IntelMP::Processor::writeOut(
-        FunctionalPort * port, Addr addr, uint8_t &checkSum)
+        PortProxy * port, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(port, addr, checkSum);
     checkSum += writeOutField(port, addr + 1, localApicID);
@@ -271,8 +271,8 @@
     checkSum += writeOutField(port, addr + 8, featureFlags);
 
     uint32_t reserved = 0;
-    port->writeBlob(addr + 12, (uint8_t *)(&reserved), 4);
-    port->writeBlob(addr + 16, (uint8_t *)(&reserved), 4);
+    port->writeMem(addr + 12, (uint8_t *)(&reserved), 4);
+    port->writeMem(addr + 16, (uint8_t *)(&reserved), 4);
     return 20;
 }
 
@@ -298,7 +298,7 @@
 
 Addr
 X86ISA::IntelMP::Bus::writeOut(
-        FunctionalPort * port, Addr addr, uint8_t &checkSum)
+        PortProxy * port, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(port, addr, checkSum);
     checkSum += writeOutField(port, addr + 1, busID);
@@ -318,7 +318,7 @@
 
 Addr
 X86ISA::IntelMP::IOAPIC::writeOut(
-        FunctionalPort * port, Addr addr, uint8_t &checkSum)
+        PortProxy * port, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(port, addr, checkSum);
     checkSum += writeOutField(port, addr + 1, id);
@@ -343,7 +343,7 @@
 
 Addr
 X86ISA::IntelMP::IntAssignment::writeOut(
-        FunctionalPort * port, Addr addr, uint8_t &checkSum)
+        PortProxy * port, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(port, addr, checkSum);
     checkSum += writeOutField(port, addr + 1, interruptType);
@@ -381,7 +381,7 @@
 
 Addr
 X86ISA::IntelMP::AddrSpaceMapping::writeOut(
-        FunctionalPort * port, Addr addr, uint8_t &checkSum)
+        PortProxy * port, Addr addr, uint8_t &checkSum)
 {
     ExtConfigEntry::writeOut(port, addr, checkSum);
     checkSum += writeOutField(port, addr + 2, busID);
@@ -405,7 +405,7 @@
 
 Addr
 X86ISA::IntelMP::BusHierarchy::writeOut(
-        FunctionalPort * port, Addr addr, uint8_t &checkSum)
+        PortProxy * port, Addr addr, uint8_t &checkSum)
 {
     ExtConfigEntry::writeOut(port, addr, checkSum);
     checkSum += writeOutField(port, addr + 2, busID);
@@ -413,7 +413,7 @@
     checkSum += writeOutField(port, addr + 4, parentBus);
 
     uint32_t reserved = 0;
-    port->writeBlob(addr + 5, (uint8_t *)(&reserved), 3);
+    port->writeMem(addr + 5, (uint8_t *)(&reserved), 3);
 
     return length;
 }
@@ -434,7 +434,7 @@
 
 Addr
 X86ISA::IntelMP::CompatAddrSpaceMod::writeOut(
-        FunctionalPort * port, Addr addr, uint8_t &checkSum)
+        PortProxy * port, Addr addr, uint8_t &checkSum)
 {
     ExtConfigEntry::writeOut(port, addr, checkSum);
     checkSum += writeOutField(port, addr + 2, busID);
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/bios/smbios.hh
--- a/src/arch/x86/bios/smbios.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/bios/smbios.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -51,7 +51,7 @@
 #include "enums/ExtCharacteristic.hh"
 #include "sim/sim_object.hh"
 
-class FunctionalPort;
+class PortProxy;
 class X86SMBiosBiosInformationParams;
 class X86SMBiosSMBiosStructureParams;
 class X86SMBiosSMBiosTableParams;
@@ -89,7 +89,7 @@
         return 4;
     }
 
-    virtual uint16_t writeOut(FunctionalPort * port, Addr addr);
+    virtual uint16_t writeOut(PortProxy * port, Addr addr);
 
   protected:
     bool stringFields;
@@ -98,7 +98,7 @@
 
     std::vector<std::string> strings;
 
-    void writeOutStrings(FunctionalPort * port, Addr addr);
+    void writeOutStrings(PortProxy * port, Addr addr);
 
     int getStringLength();
 
@@ -145,7 +145,7 @@
     BiosInformation(Params * p);
 
     uint8_t getLength() { return 0x18; }
-    uint16_t writeOut(FunctionalPort * port, Addr addr);
+    uint16_t writeOut(PortProxy * port, Addr addr);
 };
 
 class SMBiosTable : public SimObject
@@ -223,7 +223,7 @@
         smbiosHeader.intermediateHeader.tableAddr = addr;
     }
 
-    void writeOut(FunctionalPort * port, Addr addr,
+    void writeOut(PortProxy * port, Addr addr,
             Addr &headerSize, Addr &structSize);
 };
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/bios/smbios.cc
--- a/src/arch/x86/bios/smbios.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/bios/smbios.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -43,7 +43,7 @@
 #include "arch/x86/bios/smbios.hh"
 #include "arch/x86/isa_traits.hh"
 #include "base/types.hh"
-#include "mem/port.hh"
+#include "mem/port_proxy.hh"
 #include "params/X86SMBiosBiosInformation.hh"
 #include "params/X86SMBiosSMBiosStructure.hh"
 #include "params/X86SMBiosSMBiosTable.hh"
@@ -74,15 +74,15 @@
 }
 
 uint16_t
-X86ISA::SMBios::SMBiosStructure::writeOut(FunctionalPort * port, Addr addr)
+X86ISA::SMBios::SMBiosStructure::writeOut(PortProxy * port, Addr addr)
 {
-    port->writeBlob(addr, (uint8_t *)(&type), 1);
+    port->writeMem(addr, (uint8_t *)(&type), 1);
 
     uint8_t length = getLength();
-    port->writeBlob(addr + 1, (uint8_t *)(&length), 1);
+    port->writeMem(addr + 1, (uint8_t *)(&length), 1);
 
     uint16_t handleGuest = X86ISA::htog(handle);
-    port->writeBlob(addr + 2, (uint8_t *)(&handleGuest), 2);
+    port->writeMem(addr + 2, (uint8_t *)(&handleGuest), 2);
 
     return length + getStringLength();
 }
@@ -93,7 +93,7 @@
 
 void
 X86ISA::SMBios::SMBiosStructure::writeOutStrings(
-        FunctionalPort * port, Addr addr)
+        PortProxy * port, Addr addr)
 {
     std::vector<std::string>::iterator it;
     Addr offset = 0;
@@ -103,16 +103,16 @@
     // If there are string fields but none of them are used, that's a
     // special case which is handled by this if.
     if (strings.size() == 0 && stringFields) {
-        port->writeBlob(addr + offset, (uint8_t *)(&nullTerminator), 1);
+        port->writeMem(addr + offset, (uint8_t *)(&nullTerminator), 1);
         offset++;
     } else {
         for (it = strings.begin(); it != strings.end(); it++) {
-            port->writeBlob(addr + offset,
+            port->writeMem(addr + offset,
                     (uint8_t *)it->c_str(), it->length() + 1);
             offset += it->length() + 1;
         }
     }
-    port->writeBlob(addr + offset, (uint8_t *)(&nullTerminator), 1);
+    port->writeMem(addr + offset, (uint8_t *)(&nullTerminator), 1);
 }
 
 int
@@ -172,30 +172,30 @@
     }
 
 uint16_t
-X86ISA::SMBios::BiosInformation::writeOut(FunctionalPort * port, Addr addr)
+X86ISA::SMBios::BiosInformation::writeOut(PortProxy * port, Addr addr)
 {
     uint8_t size = SMBiosStructure::writeOut(port, addr);
 
-    port->writeBlob(addr + 0x4, (uint8_t *)(&vendor), 1);
-    port->writeBlob(addr + 0x5, (uint8_t *)(&version), 1);
+    port->writeMem(addr + 0x4, (uint8_t *)(&vendor), 1);
+    port->writeMem(addr + 0x5, (uint8_t *)(&version), 1);
 
     uint16_t startingAddrSegmentGuest = X86ISA::htog(startingAddrSegment);
-    port->writeBlob(addr + 0x6, (uint8_t *)(&startingAddrSegmentGuest), 2);
+    port->writeMem(addr + 0x6, (uint8_t *)(&startingAddrSegmentGuest), 2);
 
-    port->writeBlob(addr + 0x8, (uint8_t *)(&releaseDate), 1);
-    port->writeBlob(addr + 0x9, (uint8_t *)(&romSize), 1);
+    port->writeMem(addr + 0x8, (uint8_t *)(&releaseDate), 1);
+    port->writeMem(addr + 0x9, (uint8_t *)(&romSize), 1);
 
     uint64_t characteristicsGuest = X86ISA::htog(characteristics);
-    port->writeBlob(addr + 0xA, (uint8_t *)(&characteristicsGuest), 8);
+    port->writeMem(addr + 0xA, (uint8_t *)(&characteristicsGuest), 8);
 
     uint16_t characteristicExtBytesGuest =
         X86ISA::htog(characteristicExtBytes);
-    port->writeBlob(addr + 0x12, (uint8_t *)(&characteristicExtBytesGuest), 2);
+    port->writeMem(addr + 0x12, (uint8_t *)(&characteristicExtBytesGuest), 2);
 
-    port->writeBlob(addr + 0x14, (uint8_t *)(&majorVer), 1);
-    port->writeBlob(addr + 0x15, (uint8_t *)(&minorVer), 1);
-    port->writeBlob(addr + 0x16, (uint8_t *)(&embContFirmwareMajor), 1);
-    port->writeBlob(addr + 0x17, (uint8_t *)(&embContFirmwareMinor), 1);
+    port->writeMem(addr + 0x14, (uint8_t *)(&majorVer), 1);
+    port->writeMem(addr + 0x15, (uint8_t *)(&minorVer), 1);
+    port->writeMem(addr + 0x16, (uint8_t *)(&embContFirmwareMajor), 1);
+    port->writeMem(addr + 0x17, (uint8_t *)(&embContFirmwareMinor), 1);
 
     writeOutStrings(port, addr + getLength());
 
@@ -214,7 +214,7 @@
 }
 
 void
-X86ISA::SMBios::SMBiosTable::writeOut(FunctionalPort * port, Addr addr,
+X86ISA::SMBios::SMBiosTable::writeOut(PortProxy * port, Addr addr,
         Addr &headerSize, Addr &structSize)
 {
     headerSize = 0x1F;
@@ -224,26 +224,26 @@
      */
     uint8_t mainChecksum = 0;
 
-    port->writeBlob(addr, (uint8_t *)smbiosHeader.anchorString, 4);
+    port->writeMem(addr, (uint8_t *)smbiosHeader.anchorString, 4);
     for (int i = 0; i < 4; i++)
         mainChecksum += smbiosHeader.anchorString[i];
 
     // The checksum goes here, but we're figuring it out as we go.
 
-    port->writeBlob(addr + 0x5,
+    port->writeMem(addr + 0x5,
             (uint8_t *)(&smbiosHeader.entryPointLength), 1);
     mainChecksum += smbiosHeader.entryPointLength;
-    port->writeBlob(addr + 0x6,
+    port->writeMem(addr + 0x6,
             (uint8_t *)(&smbiosHeader.majorVersion), 1);
     mainChecksum += smbiosHeader.majorVersion;
-    port->writeBlob(addr + 0x7,
+    port->writeMem(addr + 0x7,
             (uint8_t *)(&smbiosHeader.minorVersion), 1);
     mainChecksum += smbiosHeader.minorVersion;
     // Maximum structure size goes here, but we'll figure it out later.
-    port->writeBlob(addr + 0xA,
+    port->writeMem(addr + 0xA,
             (uint8_t *)(&smbiosHeader.entryPointRevision), 1);
     mainChecksum += smbiosHeader.entryPointRevision;
-    port->writeBlob(addr + 0xB,
+    port->writeMem(addr + 0xB,
             (uint8_t *)(&smbiosHeader.formattedArea), 5);
     for (int i = 0; i < 5; i++)
         mainChecksum += smbiosHeader.formattedArea[i];
@@ -253,7 +253,7 @@
      */
     uint8_t intChecksum = 0;
 
-    port->writeBlob(addr + 0x10,
+    port->writeMem(addr + 0x10,
             (uint8_t *)smbiosHeader.intermediateHeader.anchorString, 5);
     for (int i = 0; i < 5; i++)
         intChecksum += smbiosHeader.intermediateHeader.anchorString[i];
@@ -263,20 +263,20 @@
 
     uint32_t tableAddrGuest =
         X86ISA::htog(smbiosHeader.intermediateHeader.tableAddr);
-    port->writeBlob(addr + 0x18, (uint8_t *)(&tableAddrGuest), 4);
+    port->writeMem(addr + 0x18, (uint8_t *)(&tableAddrGuest), 4);
     for (int i = 0; i < 4; i++) {
         intChecksum += tableAddrGuest;
         tableAddrGuest >>= 8;
     }
 
     uint16_t numStructs = X86ISA::gtoh(structures.size());
-    port->writeBlob(addr + 0x1C, (uint8_t *)(&numStructs), 2);
+    port->writeMem(addr + 0x1C, (uint8_t *)(&numStructs), 2);
     for (int i = 0; i < 2; i++) {
         intChecksum += numStructs;
         numStructs >>= 8;
     }
 
-    port->writeBlob(addr + 0x1E,
+    port->writeMem(addr + 0x1E,
             (uint8_t *)(&smbiosHeader.intermediateHeader.smbiosBCDRevision),
             1);
     intChecksum += smbiosHeader.intermediateHeader.smbiosBCDRevision;
@@ -303,7 +303,7 @@
      */
 
     maxSize = X86ISA::htog(maxSize);
-    port->writeBlob(addr + 0x8, (uint8_t *)(&maxSize), 2);
+    port->writeMem(addr + 0x8, (uint8_t *)(&maxSize), 2);
     for (int i = 0; i < 2; i++) {
         mainChecksum += maxSize;
         maxSize >>= 8;
@@ -311,7 +311,7 @@
 
     // Set the checksum
     mainChecksum = -mainChecksum;
-    port->writeBlob(addr + 0x4, (uint8_t *)(&mainChecksum), 1);
+    port->writeMem(addr + 0x4, (uint8_t *)(&mainChecksum), 1);
 
     /*
      * Intermediate header
@@ -319,14 +319,14 @@
 
     uint16_t tableSize = offset;
     tableSize = X86ISA::htog(tableSize);
-    port->writeBlob(addr + 0x16, (uint8_t *)(&tableSize), 2);
+    port->writeMem(addr + 0x16, (uint8_t *)(&tableSize), 2);
     for (int i = 0; i < 2; i++) {
         intChecksum += tableSize;
         tableSize >>= 8;
     }
 
     intChecksum = -intChecksum;
-    port->writeBlob(addr + 0x15, (uint8_t *)(&intChecksum), 1);
+    port->writeMem(addr + 0x15, (uint8_t *)(&intChecksum), 1);
 }
 
 X86ISA::SMBios::BiosInformation *
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/linux/system.cc
--- a/src/arch/x86/linux/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/linux/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -44,6 +44,7 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "mem/physical.hh"
+#include "mem/port_proxy.hh"
 #include "params/LinuxX86System.hh"
 #include "sim/byteswap.hh"
 
@@ -68,7 +69,7 @@
     const Addr realModeData = 0x90200;
 
     // A port to write to memory.
-    FunctionalPort * physPort = threadContexts[0]->getPhysPort();
+    PortProxy * physPort = threadContexts[0]->getPortProxy();
 
     /*
      * Deal with the command line stuff.
@@ -82,14 +83,14 @@
     if (commandLine.length() + 1 > realModeData - commandLineBuff)
         panic("Command line \"%s\" is longer than %d characters.\n",
                 commandLine, realModeData - commandLineBuff - 1);
-    physPort->writeBlob(commandLineBuff,
+    physPort->writeMem(commandLineBuff,
             (uint8_t *)commandLine.c_str(), commandLine.length() + 1);
 
     // Generate a pointer of the right size and endianness to put into
     // commandLinePointer.
     uint32_t guestCommandLineBuff =
         X86ISA::htog((uint32_t)commandLineBuff);
-    physPort->writeBlob(commandLinePointer,
+    physPort->writeMem(commandLinePointer,
             (uint8_t *)&guestCommandLineBuff, sizeof(guestCommandLineBuff));
 
     /*
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/process.cc
--- a/src/arch/x86/process.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/process.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -53,7 +53,6 @@
 #include "cpu/thread_context.hh"
 #include "debug/Stack.hh"
 #include "mem/page_table.hh"
-#include "mem/translating_port.hh"
 #include "sim/process_impl.hh"
 #include "sim/syscall_emul.hh"
 #include "sim/system.hh"
diff -r d00c1675ac53 -r 9ed481d9c0fb src/arch/x86/system.cc
--- a/src/arch/x86/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/arch/x86/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -49,6 +49,7 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "mem/physical.hh"
+#include "mem/port_proxy.hh"
 #include "params/X86System.hh"
 #include "sim/byteswap.hh"
 
@@ -139,7 +140,7 @@
     const int PDTBits = 9;
 
     // Get a port to write the page tables and descriptor tables.
-    FunctionalPort * physPort = tc->getPhysPort();
+    PortProxy * physPort = tc->getPortProxy();
 
     /*
      * Set up the gdt.
@@ -147,7 +148,7 @@
     uint8_t numGDTEntries = 0;
     // Place holder at selector 0
     uint64_t nullDescriptor = 0;
-    physPort->writeBlob(GDTBase + numGDTEntries * 8,
+    physPort->writeMem(GDTBase + numGDTEntries * 8,
             (uint8_t *)(&nullDescriptor), 8);
     numGDTEntries++;
 
@@ -169,7 +170,7 @@
     //it's beginning in memory and it's actual data, we'll use an
     //intermediary.
     uint64_t csDescVal = csDesc;
-    physPort->writeBlob(GDTBase + numGDTEntries * 8,
+    physPort->writeMem(GDTBase + numGDTEntries * 8,
             (uint8_t *)(&csDescVal), 8);
 
     numGDTEntries++;
@@ -192,7 +193,7 @@
     dsDesc.limitHigh = 0xF;
     dsDesc.limitLow = 0xFF;
     uint64_t dsDescVal = dsDesc;
-    physPort->writeBlob(GDTBase + numGDTEntries * 8,
+    physPort->writeMem(GDTBase + numGDTEntries * 8,
             (uint8_t *)(&dsDescVal), 8);
 
     numGDTEntries++;
@@ -220,7 +221,7 @@
     tssDesc.limitHigh = 0xF;
     tssDesc.limitLow = 0xFF;
     uint64_t tssDescVal = tssDesc;
-    physPort->writeBlob(GDTBase + numGDTEntries * 8,
+    physPort->writeMem(GDTBase + numGDTEntries * 8,
             (uint8_t *)(&tssDescVal), 8);
 
     numGDTEntries++;
@@ -250,24 +251,24 @@
     // read/write, user, not present
     uint64_t pml4e = X86ISA::htog(0x6);
     for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
-        physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
+        physPort->writeMem(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
     }
     // Point to the only PDPT
     pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
-    physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
+    physPort->writeMem(PageMapLevel4, (uint8_t *)(&pml4e), 8);
 
     // Page Directory Pointer Table
 
     // read/write, user, not present
     uint64_t pdpe = X86ISA::htog(0x6);
     for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
-        physPort->writeBlob(PageDirPtrTable + offset,
+        physPort->writeMem(PageDirPtrTable + offset,
                 (uint8_t *)(&pdpe), 8);
     }
     // Point to the PDTs
     for (int table = 0; table < NumPDTs; table++) {
         pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
-        physPort->writeBlob(PageDirPtrTable + table * 8,
+        physPort->writeMem(PageDirPtrTable + table * 8,
                 (uint8_t *)(&pdpe), 8);
     }
 
@@ -279,7 +280,7 @@
         for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
             // read/write, user, present, 4MB
             uint64_t pdte = X86ISA::htog(0x87 | base);
-            physPort->writeBlob(PageDirTable[table] + offset,
+            physPort->writeMem(PageDirTable[table] + offset,
                     (uint8_t *)(&pdte), 8);
             base += pageSize;
         }
@@ -343,7 +344,7 @@
         Addr &headerSize, Addr &structSize, Addr table)
 {
     // Get a port to write the table and header to memory.
-    FunctionalPort * physPort = threadContexts[0]->getPhysPort();
+    PortProxy * physPort = threadContexts[0]->getPortProxy();
 
     // If the table location isn't specified, just put it after the header.
     // The header size as of the 2.5 SMBios specification is 0x1F bytes
@@ -364,7 +365,7 @@
         Addr &fpSize, Addr &tableSize, Addr table)
 {
     // Get a port to write the table and header to memory.
-    FunctionalPort * physPort = threadContexts[0]->getPhysPort();
+    PortProxy * physPort = threadContexts[0]->getPortProxy();
 
     // If the table location isn't specified and it exists, just put
     // it after the floating pointer. The fp size as of the 1.4 Intel MP
diff -r d00c1675ac53 -r 9ed481d9c0fb src/base/loader/elf_object.hh
--- a/src/base/loader/elf_object.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/base/loader/elf_object.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -65,7 +65,7 @@
   public:
     virtual ~ElfObject() {}
 
-    bool loadSections(Port *memPort,
+    bool loadSections(PortProxy *memProxy,
             Addr addrMask = std::numeric_limits<Addr>::max());
     virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask =
             std::numeric_limits<Addr>::max());
diff -r d00c1675ac53 -r 9ed481d9c0fb src/base/loader/elf_object.cc
--- a/src/base/loader/elf_object.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/base/loader/elf_object.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -414,15 +414,15 @@
 }
 
 bool
-ElfObject::loadSections(Port *memPort, Addr addrMask)
+ElfObject::loadSections(PortProxy *memProxy, Addr addrMask)
 {
-    if (!ObjectFile::loadSections(memPort, addrMask))
+    if (!ObjectFile::loadSections(memProxy, addrMask))
         return false;
 
     vector<Segment>::iterator extraIt;
     for (extraIt = extraSegments.begin();
             extraIt != extraSegments.end(); extraIt++) {
-        if (!loadSection(&(*extraIt), memPort, addrMask)) {
+        if (!loadSection(&(*extraIt), memProxy, addrMask)) {
             return false;
         }
     }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/base/loader/hex_file.hh
--- a/src/base/loader/hex_file.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/base/loader/hex_file.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -37,7 +37,7 @@
 
 #include "base/types.hh"
 
-class Port;
+class PortProxy;
 
 class HexFile
 {
@@ -52,7 +52,7 @@
     virtual ~HexFile();
 
     void close();
-    bool loadSections(Port *memPort);
+    bool loadSections(PortProxy *memProxy);
 };
 
 #endif // __BASE_LOADER_HEX_FILE_HH__
diff -r d00c1675ac53 -r 9ed481d9c0fb src/base/loader/hex_file.cc
--- a/src/base/loader/hex_file.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/base/loader/hex_file.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -36,7 +36,7 @@
 #include "base/loader/hex_file.hh"
 #include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
-#include "mem/translating_port.hh"
+#include "mem/port_proxy.hh"
 
 using namespace std;
 /*
@@ -59,7 +59,7 @@
 }
 
 bool
-HexFile::loadSections(Port *memPort)
+HexFile::loadSections(PortProxy *memProxy)
 {
     char Line[64];
     Addr MemAddr;
@@ -71,7 +71,7 @@
         parseLine(Line, &MemAddr, &Data);
         if (MemAddr != 0) {
             // Now, write to memory
-            memPort->writeBlob(MemAddr << 2, (uint8_t *)&Data, sizeof(Data));
+            memProxy->writeMem(MemAddr << 2, (uint8_t *)&Data, sizeof(Data));
         }
     }
     return true;
diff -r d00c1675ac53 -r 9ed481d9c0fb src/base/loader/object_file.hh
--- a/src/base/loader/object_file.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/base/loader/object_file.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -84,8 +84,6 @@
 
     void close();
 
-    virtual bool loadSections(Port *memPort, Addr addrMask =
-            std::numeric_limits<Addr>::max());
     virtual bool loadSections(PortProxy *memProxy, Addr addrMask =
             std::numeric_limits<Addr>::max());
     virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask =
@@ -114,7 +112,6 @@
     Section data;
     Section bss;
 
-    bool loadSection(Section *sec, Port *memPort, Addr addrMask);
     bool loadSection(Section *sec, PortProxy *memProxy, Addr addrMask);
     void setGlobalPointer(Addr global_ptr) { globalPtr = global_ptr; }
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/base/loader/object_file.cc
--- a/src/base/loader/object_file.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/base/loader/object_file.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -45,7 +45,6 @@
 #include "base/loader/raw_object.hh"
 #include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
-#include "mem/translating_port.hh"
 #include "mem/port_proxy.hh"
 
 using namespace std;
@@ -64,23 +63,6 @@
     close();
 }
 
-
-bool
-ObjectFile::loadSection(Section *sec, Port *memPort, Addr addrMask)
-{
-    if (sec->size != 0) {
-        Addr addr = sec->baseAddr & addrMask;
-        if (sec->fileImage) {
-            memPort->writeBlob(addr, sec->fileImage, sec->size);
-        }
-        else {
-            // no image: must be bss
-            memPort->memsetBlob(addr, 0, sec->size);
-        }
-    }
-    return true;
-}
-
 bool
 ObjectFile::loadSection(Section *sec, PortProxy *memProxy, Addr addrMask)
 {
@@ -98,14 +80,6 @@
 }
 
 bool
-ObjectFile::loadSections(Port *memPort, Addr addrMask)
-{
-    return (loadSection(&text, memPort, addrMask)
-            && loadSection(&data, memPort, addrMask)
-            && loadSection(&bss, memPort, addrMask));
-}
-
-bool
 ObjectFile::loadSections(PortProxy *memProxy, Addr addrMask)
 {
     return (loadSection(&text, memProxy, addrMask)
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/checker/thread_context.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -97,7 +97,7 @@
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }
 
-    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+    PortProxy *getPortProxy() { return actualTC->getPortProxy(); }
 
     FSTranslatingProxy *getVirtProxy()
     { return actualTC->getVirtProxy(); }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/inorder/cpu.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -53,7 +53,6 @@
 #include "debug/RefCount.hh"
 #include "debug/SkedCache.hh"
 #include "debug/Quiesce.hh"
-#include "mem/translating_port.hh"
 #include "params/InOrderCPU.hh"
 #include "sim/process.hh"
 #include "sim/stat_control.hh"
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/inorder/thread_context.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -118,7 +118,7 @@
     TheISA::Kernel::Statistics *getKernelStats()
     { return thread->kernelStats; }
 
-    FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+    PortProxy *getPortProxy() { return thread->getPortProxy(); }
 
     FSTranslatingProxy *getVirtProxy();
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/o3/thread_context.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -97,7 +97,7 @@
     virtual TheISA::Kernel::Statistics *getKernelStats()
     { return thread->kernelStats; }
 
-    virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+    virtual PortProxy *getPortProxy() { return thread->getPortProxy(); }
 
     virtual FSTranslatingProxy *getVirtProxy();
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/ozone/cpu.hh
--- a/src/cpu/ozone/cpu.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/ozone/cpu.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -124,7 +124,7 @@
         TheISA::Kernel::Statistics *getKernelStats()
         { return thread->getKernelStats(); }
 
-        FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+        PortProxy *getPortProxy() { return thread->getPortProxy(); }
 
         FSTranslatingProxy *getVirtProxy()
         { return thread->getVirtProxy(); }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/ozone/cpu_impl.hh
--- a/src/cpu/ozone/cpu_impl.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/ozone/cpu_impl.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -195,23 +195,14 @@
     backEnd->renameTable.copyFrom(thread.renameTable);
 
 #if FULL_SYSTEM
-    Port *mem_port;
-    FunctionalPort *phys_port;
+    PortProxy *phys_proxy;
     FSTranslatingProxy *virt_proxy;
-    phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
-                                            name(), 0));
-    mem_port = system->physmem->getPort("functional");
-    mem_port->setPeer(phys_port);
-    phys_port->setPeer(mem_port);
+    phys_proxy = new PortProxy(this->getPort("dcache_port"));
 
-    virt_proxy = new FSTranslatingProxy(csprintf("%s-%d-vport",
-                                         name(), 0));
-    //mem_port = system->physmem->getPort("functional");
-    //mem_port->setPeer(virt_port);
-    //virt_port->setPeer(mem_port);
+    virt_proxy = new FSTranslatingProxy(thread.tc);
 
-    thread.setPhysPort(phys_port);
-    thread.setVirtPort(virt_port);
+    thread.setPhysPort(phys_proxy);
+    thread.setVirtPort(virt_proxy);
 #endif
 
     DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/simple_thread.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -58,7 +58,7 @@
 
 class FunctionProfile;
 class ProfileNode;
-class FunctionalPort;
+class PortProxy;
 class PhysicalPort;
 
 namespace TheISA {
@@ -208,13 +208,13 @@
     System *getSystemPtr() { return system; }
 
 #if FULL_SYSTEM
-    FunctionalPort *getPhysPort() { return physPort; }
+    PortProxy *getPortProxy() { return physPort; }
 
     /** Return a virtual port. This port cannot be cached locally in an object.
      * After a CPU switch it may point to the wrong memory object which could
      * mean stale data.
      */
-    FSTranslatingProxy *getVirtProxy() { return virtPort; }
+    FSTranslatingProxy *getVirtProxy() { return virtProxy; }
 #endif
 
     Status status() const { return _status; }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/simple_thread.cc
--- a/src/cpu/simple_thread.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/simple_thread.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -54,7 +54,6 @@
 #include "sim/serialize.hh"
 #include "sim/sim_exit.hh"
 #else
-#include "mem/translating_port.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
 #endif
@@ -119,7 +118,7 @@
 {
 #if FULL_SYSTEM
     delete physPort;
-    delete virtPort;
+    delete virtProxy;
 #endif
     delete tc;
 }
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/thread_context.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -51,7 +51,7 @@
 class Decoder;
 class EndQuiesceEvent;
 class SETranslatingProxy;
-class FunctionalPort;
+class PortProxy;
 class FSTranslatingProxy;
 class Process;
 class System;
@@ -128,7 +128,7 @@
 #if FULL_SYSTEM
     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 
-    virtual FunctionalPort *getPhysPort() = 0;
+    virtual PortProxy *getPortProxy() = 0;
 
     virtual FSTranslatingProxy *getVirtProxy() = 0;
 
@@ -298,7 +298,7 @@
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }
 
-    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+    PortProxy *getPortProxy() { return actualTC->getPortProxy(); }
 
     FSTranslatingProxy *getVirtProxy() { return actualTC->getVirtProxy(); }
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/thread_state.hh
--- a/src/cpu/thread_state.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/thread_state.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -109,11 +109,11 @@
 
     TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
 
-    FunctionalPort *getPhysPort() { return physPort; }
+    PortProxy *getPortProxy() { return physPort; }
 
-    void setPhysPort(FunctionalPort *port) { physPort = port; }
+    void setPhysPort(PortProxy *port) { physPort = port; }
 
-    FSTranslatingProxy *getVirtProxy() { return virtPort; }
+    FSTranslatingProxy *getVirtProxy() { return virtProxy; }
 #else
     Process *getProcessPtr() { return process; }
 
@@ -188,11 +188,11 @@
   protected:
     /** A functional port outgoing only for functional accesses to physical
      * addresses.*/
-    FunctionalPort *physPort;
+    PortProxy *physPort;
 
     /** A functional port, outgoing only, for functional accesse to virtual
      * addresses. */
-    FSTranslatingProxy *virtPort;
+    FSTranslatingProxy *virtProxy;
 #else
     SETranslatingProxy *port;
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/cpu/thread_state.cc
--- a/src/cpu/thread_state.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/cpu/thread_state.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -33,6 +33,7 @@
 #include "cpu/profile.hh"
 #include "cpu/thread_state.hh"
 #include "mem/port.hh"
+#include "mem/port_proxy.hh"
 #include "mem/se_translating_proxy.hh"
 #include "sim/serialize.hh"
 
@@ -51,7 +52,7 @@
       baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
 #if FULL_SYSTEM
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
-      kernelStats(NULL), physPort(NULL), virtPort(NULL),
+      kernelStats(NULL), physPort(NULL), virtProxy(NULL),
 #else
       port(NULL), process(_process),
 #endif
@@ -114,22 +115,15 @@
 void
 ThreadState::connectPhysPort()
 {
-    // @todo: For now this disregards any older port that may have
-    // already existed.  Fix this memory leak once the bus port IDs
-    // for functional ports is resolved.
-    if (physPort)
-        physPort->removeConn();
-    else
-        physPort = new FunctionalPort(csprintf("%s-%d-funcport",
-                                           baseCpu->name(), _threadId));
-    connectToMemFunc(physPort);
+    if (!physPort)
+        physPort = new PortProxy(baseCpu->getPort("dcache_port"));
 }
 
 void
 ThreadState::connectVirtPort(ThreadContext *tc)
 {
-    if (virtPort == NULL)
-        virtPort = new FSTranslatingProxy(tc);
+    if (virtProxy == NULL)
+        virtProxy = new FSTranslatingProxy(tc);
 }
 
 void
diff -r d00c1675ac53 -r 9ed481d9c0fb src/dev/simple_disk.cc
--- a/src/dev/simple_disk.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/dev/simple_disk.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -46,7 +46,7 @@
 #include "debug/SimpleDiskData.hh"
 #include "dev/disk_image.hh"
 #include "dev/simple_disk.hh"
-#include "mem/port.hh"
+#include "mem/port_proxy.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -70,7 +70,7 @@
     for (int i = 0, j = 0; i < count; i += SectorSize, j++)
         image->read(data + i, block + j);
 
-    system->functionalPort->writeBlob(addr, data, count);
+    system->initProxy->writeMem(addr, data, count);
 
     DPRINTF(SimpleDisk, "read  block=%#x len=%d\n", (uint64_t)block, count);
     DDUMP(SimpleDiskData, data, count);
diff -r d00c1675ac53 -r 9ed481d9c0fb src/kern/tru64/tru64_events.cc
--- a/src/kern/tru64/tru64_events.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/kern/tru64/tru64_events.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -62,7 +62,9 @@
     AddrRangeIter iter;
     bool found = false;
 
-    tc->getPhysPort()->getPeerAddressRanges(resp, snoop);
+    Port* dataPort = tc->getCpuPtr()->getPort("dcache_port");
+
+    dataPort->getPeerAddressRanges(resp, snoop);
     for (iter = resp.begin(); iter != resp.end(); iter++) {
         if (*iter == (K0Seg2Phys(a0) & PAddrImplMask))
             found = true;
diff -r d00c1675ac53 -r 9ed481d9c0fb src/mem/physical.cc
--- a/src/mem/physical.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/mem/physical.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -388,14 +388,16 @@
     }
 
     if (ports[idx] != NULL) {
-        panic("PhysicalMemory::getPort: port %d already assigned", idx);
+        //panic("PhysicalMemory::getPort: port %d already assigned", idx);
+        return ports[idx];
+    } else {
+
+        MemoryPort *port =
+            new MemoryPort(csprintf("%s-port%d", name(), idx), this);
+
+        ports[idx] = port;
+        return port;
     }
-
-    MemoryPort *port =
-        new MemoryPort(csprintf("%s-port%d", name(), idx), this);
-
-    ports[idx] = port;
-    return port;
 }
 
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/mem/port.hh
--- a/src/mem/port.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/mem/port.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -255,48 +255,4 @@
     void blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd);
 };
 
-/** A simple functional port that is only meant for one way communication to
- * physical memory. It is only meant to be used to load data into memory before
- * the simulation begins.
- */
-
-class FunctionalPort : public Port
-{
-  public:
-    FunctionalPort(const std::string &_name, MemObject *_owner = NULL)
-        : Port(_name, _owner)
-    {}
-
-  protected:
-    virtual bool recvTiming(PacketPtr pkt) { panic("FuncPort is UniDir");
-        M5_DUMMY_RETURN }
-    virtual Tick recvAtomic(PacketPtr pkt) { panic("FuncPort is UniDir");
-        M5_DUMMY_RETURN }
-    virtual void recvFunctional(PacketPtr pkt) { panic("FuncPort is UniDir"); }
-    virtual void recvStatusChange(Status status) {}
-
-  public:
-    /** a write function that also does an endian conversion. */
-    template <typename T>
-    inline void writeHtoG(Addr addr, T d);
-
-    /** a read function that also does an endian conversion. */
-    template <typename T>
-    inline T readGtoH(Addr addr);
-
-    template <typename T>
-    inline void write(Addr addr, T d)
-    {
-        writeBlob(addr, (uint8_t*)&d, sizeof(T));
-    }
-
-    template <typename T>
-    inline T read(Addr addr)
-    {
-        T d;
-        readBlob(addr, (uint8_t*)&d, sizeof(T));
-        return d;
-    }
-};
-
 #endif //__MEM_PORT_HH__
diff -r d00c1675ac53 -r 9ed481d9c0fb src/mem/port_impl.hh
--- a/src/mem/port_impl.hh	Mon Nov 28 18:22:57 2011 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-#include "arch/isa_traits.hh"
-#include "config/the_isa.hh"
-#include "mem/port.hh"
-#include "sim/byteswap.hh"
-
-template <typename T>
-void
-FunctionalPort::writeHtoG(Addr addr, T d)
-{
-    d = TheISA::htog(d);
-    writeBlob(addr, (uint8_t*)&d, sizeof(T));
-}
-
-
-template <typename T>
-T
-FunctionalPort::readGtoH(Addr addr)
-{
-    T d;
-    readBlob(addr, (uint8_t*)&d, sizeof(T));
-    return TheISA::gtoh(d);
-}
-
diff -r d00c1675ac53 -r 9ed481d9c0fb src/mem/translating_port.hh
--- a/src/mem/translating_port.hh	Mon Nov 28 18:22:57 2011 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ron Dreslinski
- *          Ali Saidi
- */
-
-#ifndef __MEM_TRANSLATING_PROT_HH__
-#define __MEM_TRANSLATING_PROT_HH__
-
-#include "mem/port.hh"
-
-class PageTable;
-class Process;
-
-class TranslatingPort : public FunctionalPort
-{
-  public:
-    enum AllocType {
-        Always,
-        Never,
-        NextPage
-    };
-
-  private:
-    PageTable *pTable;
-    Process *process;
-    AllocType allocating;
-
-  public:
-    TranslatingPort(const std::string &_name,
-                    Process *p, AllocType alloc);
-    virtual ~TranslatingPort();
-
-    bool tryReadBlob(Addr addr, uint8_t *p, int size);
-    bool tryWriteBlob(Addr addr, uint8_t *p, int size);
-    bool tryMemsetBlob(Addr addr, uint8_t val, int size);
-    bool tryWriteString(Addr addr, const char *str);
-    bool tryReadString(std::string &str, Addr addr);
-
-    virtual void readBlob(Addr addr, uint8_t *p, int size);
-    virtual void writeBlob(Addr addr, uint8_t *p, int size);
-    virtual void memsetBlob(Addr addr, uint8_t val, int size);
-
-    void writeString(Addr addr, const char *str);
-    void readString(std::string &str, Addr addr);
-};
-
-#endif
diff -r d00c1675ac53 -r 9ed481d9c0fb src/mem/translating_port.cc
--- a/src/mem/translating_port.cc	Mon Nov 28 18:22:57 2011 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,199 +0,0 @@
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ron Dreslinski
- *          Steve Reinhardt
- */
-
-#include <string>
-
-#include "base/chunk_generator.hh"
-#include "config/the_isa.hh"
-#include "mem/page_table.hh"
-#include "mem/port.hh"
-#include "mem/translating_port.hh"
-#include "sim/process.hh"
-
-using namespace TheISA;
-
-TranslatingPort::TranslatingPort(const std::string &_name,
-                                 Process *p, AllocType alloc)
-    : FunctionalPort(_name), pTable(p->pTable), process(p),
-      allocating(alloc)
-{ }
-
-TranslatingPort::~TranslatingPort()
-{ }
-
-bool
-TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size)
-{
-    Addr paddr;
-    int prevSize = 0;
-
-    for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-
-        if (!pTable->translate(gen.addr(),paddr))
-            return false;
-
-        Port::readBlob(paddr, p + prevSize, gen.size());
-        prevSize += gen.size();
-    }
-
-    return true;
-}
-
-void
-TranslatingPort::readBlob(Addr addr, uint8_t *p, int size)
-{
-    if (!tryReadBlob(addr, p, size))
-        fatal("readBlob(0x%x, ...) failed", addr);
-}
-
-
-bool
-TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
-{
-
-    Addr paddr;
-    int prevSize = 0;
-
-    for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-
-        if (!pTable->translate(gen.addr(), paddr)) {
-            if (allocating == Always) {
-                process->allocateMem(roundDown(gen.addr(), VMPageSize),
-                                     VMPageSize);
-            } else if (allocating == NextPage) {
-                // check if we've accessed the next page on the stack
-                if (!process->fixupStackFault(gen.addr()))
-                    panic("Page table fault when accessing virtual address %#x "
-                            "during functional write\n", gen.addr());
-            } else {
-                return false;
-            }
-            pTable->translate(gen.addr(), paddr);
-        }
-
-        Port::writeBlob(paddr, p + prevSize, gen.size());
-        prevSize += gen.size();
-    }
-
-    return true;
-}
-
-
-void
-TranslatingPort::writeBlob(Addr addr, uint8_t *p, int size)
-{
-    if (!tryWriteBlob(addr, p, size))
-        fatal("writeBlob(0x%x, ...) failed", addr);
-}
-
-bool
-TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size)
-{
-    Addr paddr;
-
-    for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-
-        if (!pTable->translate(gen.addr(), paddr)) {
-            if (allocating == Always) {
-                process->allocateMem(roundDown(gen.addr(), VMPageSize),
-                                     VMPageSize);
-                pTable->translate(gen.addr(), paddr);
-            } else {
-                return false;
-            }
-        }
-
-        Port::memsetBlob(paddr, val, gen.size());
-    }
-
-    return true;
-}
-
-void
-TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size)
-{
-    if (!tryMemsetBlob(addr, val, size))
-        fatal("memsetBlob(0x%x, ...) failed", addr);
-}
-
-
-bool
-TranslatingPort::tryWriteString(Addr addr, const char *str)
-{
-    Addr paddr,vaddr;
-    uint8_t c;
-
-    vaddr = addr;
-
-    do {
-        c = *str++;
-        if (!pTable->translate(vaddr++,paddr))
-            return false;
-
-        Port::writeBlob(paddr, &c, 1);
-    } while (c);
-
-    return true;
-}
-
-void
-TranslatingPort::writeString(Addr addr, const char *str)
-{
-    if (!tryWriteString(addr, str))
-        fatal("writeString(0x%x, ...) failed", addr);
-}
-
-bool
-TranslatingPort::tryReadString(std::string &str, Addr addr)
-{
-    Addr paddr,vaddr;
-    uint8_t c;
-
-    vaddr = addr;
-
-    do {
-        if (!pTable->translate(vaddr++,paddr))
-            return false;
-
-        Port::readBlob(paddr, &c, 1);
-        str += c;
-    } while (c);
-
-    return true;
-}
-
-void
-TranslatingPort::readString(std::string &str, Addr addr)
-{
-    if (!tryReadString(str, addr))
-        fatal("readString(0x%x, ...) failed", addr);
-}
-
diff -r d00c1675ac53 -r 9ed481d9c0fb src/mem/vport.hh
--- a/src/mem/vport.hh	Mon Nov 28 18:22:57 2011 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-/**
- * @file
- * Virtual Port Object Declaration. These ports incorporate some translation
- * into their access methods. Thus you can use one to read and write data
- * to/from virtual addresses.
- */
-
-#ifndef __MEM_VPORT_HH__
-#define __MEM_VPORT_HH__
-
-#include "arch/vtophys.hh"
-#include "config/full_system.hh"
-#include "mem/port_impl.hh"
-
-/** A class that translates a virtual address to a physical address and then
- * calls the above read/write functions. If a thread context is provided the
- * address can alway be translated, If not it can only be translated if it is a
- * simple address masking operation (such as alpha super page accesses).
- */
-
-
-class VirtualPort  : public FunctionalPort
-{
-  private:
-    ThreadContext *tc;
-
-  public:
-    VirtualPort(const std::string &_name, ThreadContext *_tc = NULL)
-        : FunctionalPort(_name), tc(_tc)
-    {}
-
-    /** Return true if we have an thread context. This is used to
-     * prevent someone from accidently deleting the cpus statically
-     * allocated vport.
-     * @return true if a thread context isn't valid
-     */
-    bool nullThreadContext() { return tc != NULL; }
-
-    /** Version of readblob that translates virt->phys and deals
-      * with page boundries. */
-    virtual void readBlob(Addr addr, uint8_t *p, int size);
-
-    /** Version of writeBlob that translates virt->phys and deals
-      * with page boundries. */
-    virtual void writeBlob(Addr addr, uint8_t *p, int size);
-};
-
-
-void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
-void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen);
-void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
-
-#endif //__MEM_VPORT_HH__
-
diff -r d00c1675ac53 -r 9ed481d9c0fb src/mem/vport.cc
--- a/src/mem/vport.cc	Mon Nov 28 18:22:57 2011 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-/**
- * @file
- * Port object definitions.
- */
-
-#include "base/chunk_generator.hh"
-#include "config/the_isa.hh"
-#include "cpu/thread_context.hh"
-#include "mem/vport.hh"
-
-void
-VirtualPort::readBlob(Addr addr, uint8_t *p, int size)
-{
-    Addr paddr;
-    for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
-            gen.next())
-    {
-        if (tc)
-            paddr = TheISA::vtophys(tc,gen.addr());
-        else
-            paddr = TheISA::vtophys(gen.addr());
-
-        FunctionalPort::readBlob(paddr, p, gen.size());
-        p += gen.size();
-    }
-}
-
-void
-VirtualPort::writeBlob(Addr addr, uint8_t *p, int size)
-{
-    Addr paddr;
-    for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
-            gen.next())
-    {
-        if (tc)
-            paddr = TheISA::vtophys(tc,gen.addr());
-        else
-            paddr = TheISA::vtophys(gen.addr());
-
-        FunctionalPort::writeBlob(paddr, p, gen.size());
-        p += gen.size();
-    }
-}
-
-void
-CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
-{
-    uint8_t *dst = (uint8_t *)dest;
-    VirtualPort *vp = tc->getVirtPort();
-
-    vp->readBlob(src, dst, cplen);
-}
-
-void
-CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
-{
-    uint8_t *src = (uint8_t *)source;
-    VirtualPort *vp = tc->getVirtPort();
-
-    vp->writeBlob(dest, src, cplen);
-}
-
-void
-CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
-{
-    int len = 0;
-    char *start = dst;
-    VirtualPort *vp = tc->getVirtPort();
-
-    do {
-        vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
-    } while (len < maxlen && start[len++] != 0 );
-
-    dst[len] = 0;
-}
-
-void
-CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
-{
-    VirtualPort *vp = tc->getVirtPort();
-    for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();
-            gen.next())
-    {
-        vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
-        src += gen.size();
-    }
-}
diff -r d00c1675ac53 -r 9ed481d9c0fb src/sim/process_impl.hh
--- a/src/sim/process_impl.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/sim/process_impl.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -44,7 +44,6 @@
 #include <string>
 #include <vector>
 
-#include "mem/translating_port.hh"
 #include "mem/se_translating_proxy.hh"
 #include "sim/byteswap.hh"
 
diff -r d00c1675ac53 -r 9ed481d9c0fb src/sim/system.hh
--- a/src/sim/system.hh	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/sim/system.hh	Mon Nov 28 18:23:00 2011 +0000
@@ -59,7 +59,7 @@
 
 #if FULL_SYSTEM
 class Platform;
-class FunctionalPort;
+class PortProxy;
 class FSTranslatingProxy;
 #endif
 class GDBListener;
@@ -144,8 +144,8 @@
 
     /** Port to physical memory used for writing object files into ram at
      * boot.*/
-    FunctionalPort *functionalPort;
-    FSTranslatingProxy *virtPort;
+    PortProxy *initProxy;
+    FSTranslatingProxy *translatingProxy;
 
     /** kernel symbol table */
     SymbolTable *kernelSymtab;
diff -r d00c1675ac53 -r 9ed481d9c0fb src/sim/system.cc
--- a/src/sim/system.cc	Mon Nov 28 18:22:57 2011 +0000
+++ b/src/sim/system.cc	Mon Nov 28 18:23:00 2011 +0000
@@ -103,15 +103,10 @@
 
 
     /**
-     * Get a functional port to memory
+     * Get a port proxy to memory
      */
-    Port *mem_port;
-    functionalPort = new FunctionalPort(name() + "-fport");
-    mem_port = physmem->getPort("functional");
-    functionalPort->setPeer(mem_port);
-    mem_port->setPeer(functionalPort);
-
-    virtPort = new FSTranslatingProxy(systemPort());
+    initProxy = new PortProxy(systemPort());
+    translatingProxy = new FSTranslatingProxy(systemPort());
 #endif
 }
 
@@ -135,7 +130,7 @@
             fatal("Could not load kernel file %s", params()->kernel);
 
         // Load program sections into memory
-        kernel->loadSections(functionalPort, loadAddrMask);
+        kernel->loadSections(initProxy, loadAddrMask);
 
         // setup entry points
         kernelStart = kernel->textBase();