diff -r ca98021c3f96 src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh	Thu Dec 15 00:43:35 2011 -0500
+++ b/src/arch/alpha/isa_traits.hh	Thu Dec 22 19:36:43 2011 +0100
@@ -130,6 +130,9 @@
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
 
+// Ensure PC alignment
+const Addr PcAlignment = ~ULL(3);
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__
diff -r ca98021c3f96 src/arch/arm/isa_traits.hh
--- a/src/arch/arm/isa_traits.hh	Thu Dec 15 00:43:35 2011 -0500
+++ b/src/arch/arm/isa_traits.hh	Thu Dec 22 19:36:43 2011 +0100
@@ -114,6 +114,9 @@
     // Memory accesses cannot be unaligned
     const bool HasUnalignedMemAcc = true;
 
+    // Ensure PC alignment
+    const Addr PcAlignment = ~ULL(0);
+
     enum InterruptTypes
     {
         INT_RST,
diff -r ca98021c3f96 src/arch/mips/isa_traits.hh
--- a/src/arch/mips/isa_traits.hh	Thu Dec 15 00:43:35 2011 -0500
+++ b/src/arch/mips/isa_traits.hh	Thu Dec 22 19:36:43 2011 +0100
@@ -162,6 +162,9 @@
 
 const bool HasUnalignedMemAcc = true;
 
+// Ensure PC alignment
+const Addr PcAlignment = ~ULL(0);
+
 } // namespace MipsISA
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff -r ca98021c3f96 src/arch/power/isa_traits.hh
--- a/src/arch/power/isa_traits.hh	Thu Dec 15 00:43:35 2011 -0500
+++ b/src/arch/power/isa_traits.hh	Thu Dec 22 19:36:43 2011 +0100
@@ -72,6 +72,9 @@
 // Memory accesses can be unaligned
 const bool HasUnalignedMemAcc = true;
 
+// Ensure PC alignment
+const Addr PcAlignment = ~ULL(0);
+
 } // namespace PowerISA
 
 #endif // __ARCH_POWER_ISA_TRAITS_HH__
diff -r ca98021c3f96 src/arch/sparc/isa_traits.hh
--- a/src/arch/sparc/isa_traits.hh	Thu Dec 15 00:43:35 2011 -0500
+++ b/src/arch/sparc/isa_traits.hh	Thu Dec 22 19:36:43 2011 +0100
@@ -95,6 +95,9 @@
 
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
+
+// Ensure PC alignment
+const Addr PcAlignment = ~ULL(0);
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__
diff -r ca98021c3f96 src/arch/x86/isa_traits.hh
--- a/src/arch/x86/isa_traits.hh	Thu Dec 15 00:43:35 2011 -0500
+++ b/src/arch/x86/isa_traits.hh	Thu Dec 22 19:36:43 2011 +0100
@@ -74,6 +74,9 @@
     // Memory accesses can be unaligned
     const bool HasUnalignedMemAcc = true;
 
+    // Ensure PC alignment
+    const Addr PcAlignment = ~ULL(0);
+
     const ExtMachInst NoopMachInst = {
         0x0,                            // No legacy prefixes.
         0x0,                            // No rex prefix.
diff -r ca98021c3f96 src/cpu/pc_event.cc
--- a/src/cpu/pc_event.cc	Thu Dec 15 00:43:35 2011 -0500
+++ b/src/cpu/pc_event.cc	Thu Dec 22 19:36:43 2011 +0100
@@ -34,6 +34,7 @@
 #include <string>
 #include <utility>
 
+#include "arch/isa_traits.hh"
 #include "base/debug.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
@@ -84,7 +85,7 @@
 bool
 PCEventQueue::doService(ThreadContext *tc)
 {
-    Addr pc = tc->instAddr() & ~0x3;
+    Addr pc = tc->instAddr() & TheISA::PcAlignment;
     int serviced = 0;
     range_t range = equal_range(pc);
     for (iterator i = range.first; i != range.second; ++i) {
@@ -92,7 +93,7 @@
         // another event.  This for example, prevents two invocations
         // of the SkipFuncEvent.  Maybe we should have separate PC
         // event queues for each processor?
-        if (pc != (tc->instAddr() & ~0x3))
+        if (pc != (tc->instAddr() & TheISA::PcAlignment))
             continue;
 
         DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",