diff -r 1c420a04832b -r c8bd022f464d tests/configs/o3-timing-ruby.py --- a/tests/configs/o3-timing-ruby.py Sun Apr 08 11:34:34 2012 -0500 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,51 +0,0 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Steve Reinhardt - -import m5 -from m5.objects import * -m5.util.addToPath('../configs/common') - - -import ruby_config -ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) - -cpu = DerivO3CPU(cpu_id=0) -cpu.clock = '2GHz' - -system = System(cpu = cpu, - physmem = ruby_memory, - membus = Bus()) -system.physmem.port = system.membus.master -# create the interrupt controller -cpu.createInterruptController() -cpu.connectAllPorts(system.membus) - -# Connect the system port for loading of binaries etc -system.system_port = system.membus.slave - -root = Root(full_system = False, system = system) diff -r 1c420a04832b -r c8bd022f464d tests/configs/pc-simple-timing-ruby.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/configs/pc-simple-timing-ruby.py Sun Apr 08 11:34:34 2012 -0500 @@ -0,0 +1,78 @@ +# Copyright (c) 2012 Mark D. Hill and David A. Wood +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nilay Vaish + +import m5, os, optparse, sys +from m5.objects import * +m5.util.addToPath('../configs/common') +from Benchmarks import SysConfig +import FSConfig + +m5.util.addToPath('../configs/ruby') +import Ruby +import Options + +# Add the ruby specific and protocol specific options +parser = optparse.OptionParser() +Options.addCommonOptions(parser) +Ruby.define_options(parser) +(options, args) = parser.parse_args() + +# Set the default cache size and associativity to be very small to encourage +# races between requests and writebacks. +options.l1d_size="32kB" +options.l1i_size="32kB" +options.l2_size="4MB" +options.l1d_assoc=2 +options.l1i_assoc=2 +options.l2_assoc=2 +options.l3_assoc=2 +options.detailed=True + +# this is a uniprocessor only test +options.num_cpus = 1 +cpu = TimingSimpleCPU(cpu_id=0) +#the system +mdesc = SysConfig(disk = 'linux-x86.img') +system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc, Ruby=True) +system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') +system.cpu = cpu +Ruby.create_system(options, system, system.piobus, system._dma_ports) + +# create the interrupt controller +cpu.createInterruptController() +cpu.icache_port = system.ruby._cpu_ruby_ports[0].slave +cpu.dcache_port = system.ruby._cpu_ruby_ports[0].slave +cpu.itb.walker.port = system.ruby._cpu_ruby_ports[0].slave +cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[0].slave +cpu.interrupts.pio = system.piobus.master +cpu.interrupts.int_master = system.piobus.slave +cpu.interrupts.int_slave = system.piobus.master +cpu.clock = '2GHz' + +root = Root(full_system = True, system = system) +m5.ticks.setGlobalFrequency('1THz') diff -r 1c420a04832b -r c8bd022f464d tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini Sun Apr 08 11:34:34 2012 -0500 @@ -0,0 +1,1232 @@ +[root] +type=Root +children=system +full_system=true +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxX86System +children=acpi_description_table_pointer cpu dir_cntrl0 dma_cntrl0 e820_table intel_mp_pointer intel_mp_table intrctrl l1_cntrl0 l2_cntrl0 pc physmem piobus ruby smbios_table sys_port_proxy +acpi_description_table_pointer=system.acpi_description_table_pointer +boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +e820_table=system.e820_table +init_param=0 +intel_mp_pointer=system.intel_mp_pointer +intel_mp_table=system.intel_mp_table +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +load_addr_mask=18446744073709551615 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile=tests/halt.sh +smbios_table=system.smbios_table +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.acpi_description_table_pointer] +type=X86ACPIRSDP +children=xsdt +oem_id= +revision=2 +rsdt=Null +xsdt=system.acpi_description_table_pointer.xsdt + +[system.acpi_description_table_pointer.xsdt] +type=X86ACPIXSDT +creator_id= +creator_revision=0 +entries= +oem_id= +oem_revision=0 +oem_table_id= + +[system.cpu] +type=TimingSimpleCPU +children=dtb interrupts itb tracer +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload= +dcache_port=system.l1_cntrl0.sequencer.slave[1] +icache_port=system.l1_cntrl0.sequencer.slave[0] + +[system.cpu.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.slave[3] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.piobus.slave[3] +int_slave=system.piobus.master[19] +pio=system.piobus.master[18] + +[system.cpu.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.slave[2] + +[system.cpu.tracer] +type=ExeTracer + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=2 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dma_cntrl0] +type=DMA_Controller +children=dma_sequencer +buffer_size=0 +cntrl_id=3 +dma_sequencer=system.dma_cntrl0.dma_sequencer +number_of_TBEs=256 +recycle_latency=10 +request_latency=6 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dma_cntrl0.dma_sequencer] +type=DMASequencer +access_phys_mem=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +slave=system.pc.south_bridge.ide.dma + +[system.e820_table] +type=X86E820Table +children=entries0 entries1 +entries=system.e820_table.entries0 system.e820_table.entries1 + +[system.e820_table.entries0] +type=X86E820Entry +addr=0 +range_type=2 +size=1048576 + +[system.e820_table.entries1] +type=X86E820Entry +addr=1048576 +range_type=1 +size=133169152 + +[system.intel_mp_pointer] +type=X86IntelMPFloatingPointer +default_config=0 +imcr_present=true +spec_rev=4 + +[system.intel_mp_table] +type=X86IntelMPConfigTable +children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries +base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +ext_entries=system.intel_mp_table.ext_entries +local_apic=4276092928 +oem_id= +oem_table_addr=0 +oem_table_size=0 +product_id= +spec_rev=4 + +[system.intel_mp_table.base_entries00] +type=X86IntelMPProcessor +bootstrap=true +enable=true +family=0 +feature_flags=0 +local_apic_id=0 +local_apic_version=20 +model=0 +stepping=0 + +[system.intel_mp_table.base_entries01] +type=X86IntelMPIOAPIC +address=4273995776 +enable=true +id=1 +version=17 + +[system.intel_mp_table.base_entries02] +type=X86IntelMPBus +bus_id=0 +bus_type=ISA + +[system.intel_mp_table.base_entries03] +type=X86IntelMPBus +bus_id=1 +bus_type=PCI + +[system.intel_mp_table.base_entries04] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=16 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=1 +source_bus_irq=16 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries05] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=0 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries06] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=2 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=0 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries07] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=1 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries08] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=1 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=1 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries09] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=3 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries10] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=3 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=3 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries11] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=4 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries12] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=4 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=4 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries13] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=5 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries14] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=5 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=5 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries15] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=6 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries16] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=6 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=6 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries17] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=7 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries18] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=7 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=7 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries19] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=8 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries20] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=8 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=8 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries21] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=9 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries22] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=9 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=9 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries23] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=10 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries24] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=10 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=10 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries25] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=11 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries26] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=11 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=11 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries27] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=12 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries28] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=12 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=12 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries29] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=13 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries30] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=13 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=13 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries31] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=14 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries32] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=14 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=14 +trigger=ConformTrigger + +[system.intel_mp_table.ext_entries] +type=X86IntelMPBusHierarchy +bus_id=0 +parent_bus=1 +subtractive_decode=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +buffer_size=0 +cntrl_id=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=32768 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=32768 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +pio_port=system.piobus.slave[2] +slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +cntrl_id=1 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=15 +replacement_policy=PSEUDO_LRU +size=4194304 +start_index_bit=6 + +[system.pc] +type=Pc +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +intrctrl=system.intrctrl +system=system + +[system.pc.behind_pci] +type=IsaFake +fake_mem=false +pio_addr=9223372036854779128 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.piobus.master[12] + +[system.pc.com_1] +type=Uart8250 +children=terminal +pio_addr=9223372036854776824 +pio_latency=1000 +platform=system.pc +system=system +terminal=system.pc.com_1.terminal +pio=system.piobus.master[13] + +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.pc.fake_com_2] +type=IsaFake +fake_mem=false +pio_addr=9223372036854776568 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.piobus.master[14] + +[system.pc.fake_com_3] +type=IsaFake +fake_mem=false +pio_addr=9223372036854776808 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.piobus.master[15] + +[system.pc.fake_com_4] +type=IsaFake +fake_mem=false +pio_addr=9223372036854776552 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.piobus.master[16] + +[system.pc.fake_floppy] +type=IsaFake +fake_mem=false +pio_addr=9223372036854776818 +pio_latency=1000 +pio_size=2 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.piobus.master[17] + +[system.pc.i_dont_exist] +type=IsaFake +fake_mem=false +pio_addr=9223372036854775936 +pio_latency=1000 +pio_size=1 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.piobus.master[11] + +[system.pc.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=system.pc +size=16777216 +system=system +pio=system.piobus.default + +[system.pc.south_bridge] +type=SouthBridge +children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker +cmos=system.pc.south_bridge.cmos +dma1=system.pc.south_bridge.dma1 +io_apic=system.pc.south_bridge.io_apic +keyboard=system.pc.south_bridge.keyboard +pic1=system.pc.south_bridge.pic1 +pic2=system.pc.south_bridge.pic2 +pio_latency=1000 +pit=system.pc.south_bridge.pit +platform=system.pc +speaker=system.pc.south_bridge.speaker + +[system.pc.south_bridge.cmos] +type=Cmos +children=int_pin +int_pin=system.pc.south_bridge.cmos.int_pin +pio_addr=9223372036854775920 +pio_latency=1000 +system=system +time=Sun Jan 1 00:00:00 2012 +pio=system.piobus.master[1] + +[system.pc.south_bridge.cmos.int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.dma1] +type=I8237 +pio_addr=9223372036854775808 +pio_latency=1000 +system=system +pio=system.piobus.master[2] + +[system.pc.south_bridge.ide] +type=IdeController +children=disks0 disks1 +BAR0=496 +BAR0LegacyIO=true +BAR0Size=8 +BAR1=1012 +BAR1LegacyIO=true +BAR1Size=3 +BAR2=368 +BAR2LegacyIO=true +BAR2Size=8 +BAR3=884 +BAR3LegacyIO=true +BAR3Size=3 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=14 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=128 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +ctrl_offset=0 +disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +io_shift=0 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=4 +pci_func=0 +pio_latency=1000 +platform=system.pc +system=system +config=system.piobus.master[4] +dma=system.piobus.slave[0] +pio=system.piobus.master[3] + +[system.pc.south_bridge.ide.disks0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.pc.south_bridge.ide.disks0.image + +[system.pc.south_bridge.ide.disks0.image] +type=CowDiskImage +children=child +child=system.pc.south_bridge.ide.disks0.image.child +image_file= +read_only=false +table_size=65536 + +[system.pc.south_bridge.ide.disks0.image.child] +type=RawDiskImage +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +read_only=true + +[system.pc.south_bridge.ide.disks1] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.pc.south_bridge.ide.disks1.image + +[system.pc.south_bridge.ide.disks1.image] +type=CowDiskImage +children=child +child=system.pc.south_bridge.ide.disks1.image.child +image_file= +read_only=false +table_size=65536 + +[system.pc.south_bridge.ide.disks1.image.child] +type=RawDiskImage +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +read_only=true + +[system.pc.south_bridge.int_lines0] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines0.sink +source=system.pc.south_bridge.pic1.output + +[system.pc.south_bridge.int_lines0.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=0 + +[system.pc.south_bridge.int_lines1] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines1.sink +source=system.pc.south_bridge.pic2.output + +[system.pc.south_bridge.int_lines1.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic1 +number=2 + +[system.pc.south_bridge.int_lines2] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines2.sink +source=system.pc.south_bridge.cmos.int_pin + +[system.pc.south_bridge.int_lines2.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic2 +number=0 + +[system.pc.south_bridge.int_lines3] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines3.sink +source=system.pc.south_bridge.pit.int_pin + +[system.pc.south_bridge.int_lines3.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic1 +number=0 + +[system.pc.south_bridge.int_lines4] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines4.sink +source=system.pc.south_bridge.pit.int_pin + +[system.pc.south_bridge.int_lines4.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=2 + +[system.pc.south_bridge.int_lines5] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines5.sink +source=system.pc.south_bridge.keyboard.keyboard_int_pin + +[system.pc.south_bridge.int_lines5.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=1 + +[system.pc.south_bridge.int_lines6] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines6.sink +source=system.pc.south_bridge.keyboard.mouse_int_pin + +[system.pc.south_bridge.int_lines6.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=12 + +[system.pc.south_bridge.io_apic] +type=I82094AA +apic_id=1 +external_int_pic=system.pc.south_bridge.pic1 +int_latency=1000 +pio_addr=4273995776 +pio_latency=1000 +system=system +int_master=system.piobus.slave[1] +pio=system.piobus.master[10] + +[system.pc.south_bridge.keyboard] +type=I8042 +children=keyboard_int_pin mouse_int_pin +command_port=9223372036854775908 +data_port=9223372036854775904 +keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin +mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin +pio_addr=0 +pio_latency=1000 +system=system +pio=system.piobus.master[5] + +[system.pc.south_bridge.keyboard.keyboard_int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.keyboard.mouse_int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.pic1] +type=I8259 +children=output +mode=I8259Master +output=system.pc.south_bridge.pic1.output +pio_addr=9223372036854775840 +pio_latency=1000 +slave=system.pc.south_bridge.pic2 +system=system +pio=system.piobus.master[6] + +[system.pc.south_bridge.pic1.output] +type=X86IntSourcePin + +[system.pc.south_bridge.pic2] +type=I8259 +children=output +mode=I8259Slave +output=system.pc.south_bridge.pic2.output +pio_addr=9223372036854775968 +pio_latency=1000 +slave=Null +system=system +pio=system.piobus.master[7] + +[system.pc.south_bridge.pic2.output] +type=X86IntSourcePin + +[system.pc.south_bridge.pit] +type=I8254 +children=int_pin +int_pin=system.pc.south_bridge.pit.int_pin +pio_addr=9223372036854775872 +pio_latency=1000 +system=system +pio=system.piobus.master[8] + +[system.pc.south_bridge.pit.int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.speaker] +type=PcSpeaker +i8254=system.pc.south_bridge.pit +pio_addr=9223372036854775905 +pio_latency=1000 +system=system +pio=system.piobus.master[9] + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.piobus.master[0] + +[system.piobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=true +width=64 +default=system.pc.pciconfig.pio +master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.cpu.interrupts.int_master + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=500 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 routers3 routers4 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l2_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.ext_links3] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dma_cntrl0 +int_node=system.ruby.network.topology.routers3 +latency=1 +link_id=3 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=4 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers4 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers4 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=6 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers4 +weight=1 + +[system.ruby.network.topology.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=7 +node_a=system.ruby.network.topology.routers3 +node_b=system.ruby.network.topology.routers4 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers4] +type=BasicRouter +router_id=4 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.smbios_table] +type=X86SMBiosSMBiosTable +children=structures +major_version=2 +minor_version=5 +structures=system.smbios_table.structures + +[system.smbios_table.structures] +type=X86SMBiosBiosInformation +characteristic_ext_bytes= +characteristics= +emb_cont_firmware_major=0 +emb_cont_firmware_minor=0 +major=0 +minor=0 +release_date=06/08/2008 +rom_size=0 +starting_addr_segment=0 +vendor= +version= + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +slave=system.system_port + diff -r 1c420a04832b -r c8bd022f464d tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats Sun Apr 08 11:34:34 2012 -0500 @@ -0,0 +1,665 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 500 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, ordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Apr/08/2012 11:24:07 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 605 +Elapsed_time_in_minutes: 10.0833 +Elapsed_time_in_hours: 0.168056 +Elapsed_time_in_days: 0.00700231 + +Virtual_time_in_seconds: 605.05 +Virtual_time_in_minutes: 10.0842 +Virtual_time_in_hours: 0.168069 +Virtual_time_in_days: 0.00700289 + +Ruby_current_time: 10527900670 +Ruby_start_time: 0 +Ruby_cycles: 10527900670 + +mbytes_resident: 258.742 +mbytes_total: 505.492 +resident_ratio: 0.511877 + +ruby_cycles_executed: [ 10527900671 ] + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 +DMA-0:0 + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 167527124 average: 1.00006 | standard deviation: 0.00794093 | 0 167516560 10564 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 1 max: 163 count: 167527123 average: 3.38705 | standard deviation: 5.19495 | 0 0 0 165199007 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 736612 0 0 0 1434567 1 0 0 0 3 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10017 0 3 6 87269 7 15 9 59597 0 1 ] +miss_latency_LD: [binsize: 1 max: 161 count: 12758313 average: 5.35551 | standard deviation: 9.47643 | 0 0 0 11442548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60971 0 0 0 1225422 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2908 0 1 0 12264 3 1 2 14192 ] +miss_latency_ST: [binsize: 1 max: 163 count: 8352397 average: 5.5873 | standard deviation: 18.1726 | 0 0 0 8034789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16000 0 0 0 188525 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2934 0 0 0 64882 4 14 7 45238 0 1 ] +miss_latency_IFETCH: [binsize: 1 max: 157 count: 145842547 average: 3.08695 | standard deviation: 1.84874 | 0 0 0 145171264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 657089 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4164 0 2 6 10013 ] +miss_latency_RMW_Read: [binsize: 1 max: 161 count: 571134 average: 3.87013 | standard deviation: 5.20073 | 0 0 0 547731 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2545 0 0 0 20571 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 110 0 0 0 166 ] +miss_latency_Locked_RMW_Read: [binsize: 1 max: 161 count: 1366 average: 3.91508 | standard deviation: 5.75527 | 0 0 0 1309 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 49 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 1366 average: 3 | standard deviation: 0 | 0 0 0 1366 ] +miss_latency_NULL: [binsize: 1 max: 163 count: 167527123 average: 3.38705 | standard deviation: 5.19495 | 0 0 0 165199007 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 736612 0 0 0 1434567 1 0 0 0 3 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10017 0 3 6 87269 7 15 9 59597 0 1 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 1 max: 161 count: 12758313 average: 5.35551 | standard deviation: 9.47643 | 0 0 0 11442548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60971 0 0 0 1225422 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2908 0 1 0 12264 3 1 2 14192 ] +miss_latency_ST_NULL: [binsize: 1 max: 163 count: 8352397 average: 5.5873 | standard deviation: 18.1726 | 0 0 0 8034789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16000 0 0 0 188525 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2934 0 0 0 64882 4 14 7 45238 0 1 ] +miss_latency_IFETCH_NULL: [binsize: 1 max: 157 count: 145842547 average: 3.08695 | standard deviation: 1.84874 | 0 0 0 145171264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 657089 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4164 0 2 6 10013 ] +miss_latency_RMW_Read_NULL: [binsize: 1 max: 161 count: 571134 average: 3.87013 | standard deviation: 5.20073 | 0 0 0 547731 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2545 0 0 0 20571 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 110 0 0 0 166 ] +miss_latency_Locked_RMW_Read_NULL: [binsize: 1 max: 161 count: 1366 average: 3.91508 | standard deviation: 5.75527 | 0 0 0 1309 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 49 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 1366 average: 3 | standard deviation: 0 | 0 0 0 1366 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 9 count: 9884350 average: 0.63187 | standard deviation: 1.45885 | 8322948 2 0 1 1561390 6 0 0 0 3 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 5 count: 4243179 average: 8.4842e-06 | standard deviation: 0.00586585 | 4243170 0 0 1 7 1 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 9 count: 5641171 average: 1.10714 | standard deviation: 1.78965 | 4079778 2 0 0 1561383 5 0 0 0 3 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 5226 average: 0 | standard deviation: 0 | 5226 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 5 count: 4237953 average: 8.49467e-06 | standard deviation: 0.00586946 | 4237944 0 0 1 7 1 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 604 +system_time: 0 +page_reclaims: 68104 +page_faults: 64 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +total_msg_count_Control: 7455120 59640960 +total_msg_count_Request_Control: 15678 125424 +total_msg_count_Response_Data: 7694451 554000472 +total_msg_count_Response_Control: 10264053 82112424 +total_msg_count_Writeback_Data: 4684242 337265424 +total_msg_count_Writeback_Control: 284583 2276664 +total_msgs: 30398127 total_bytes: 1035421368 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 0.096772 + links_utilized_percent_switch_0_link_0: 0.107403 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0861411 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 5226 41808 [ 5226 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 2328116 167624352 [ 0 2328116 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 1656252 13250016 [ 0 1656252 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 2328116 18624928 [ 2328116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 1662006 13296048 [ 0 5203 1656803 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1561414 112421808 [ 1561391 23 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 94861 758888 [ 94861 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 0.102448 + links_utilized_percent_switch_1_link_0: 0.0932829 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.111613 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 2328116 18624928 [ 2328116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 156924 11298528 [ 0 156924 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1753441 14027528 [ 0 96638 1656803 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1561414 112421808 [ 1561391 23 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 94861 758888 [ 94861 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 156924 1255392 [ 156924 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 5226 41808 [ 5226 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 2407893 173368296 [ 0 2407893 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1667910 13343280 [ 0 1667910 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 0.00567617 + links_utilized_percent_switch_2_link_0: 0.0042106 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.00714174 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 156924 1255392 [ 156924 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 79777 5743944 [ 0 79777 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 11658 93264 [ 0 11658 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 156924 11298528 [ 0 156924 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 91435 731480 [ 0 91435 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 2 +switch_3_outlinks: 2 +links_utilized_percent_switch_3: 0 + links_utilized_percent_switch_3_link_0: 0 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0 bw: 16000 base_latency: 1 + + +switch_4_inlinks: 4 +switch_4_outlinks: 4 +links_utilized_percent_switch_4: 0.0512241 + links_utilized_percent_switch_4_link_0: 0.107403 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.0932829 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_2: 0.0042106 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_3: 0 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 5226 41808 [ 5226 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 2328116 167624352 [ 0 2328116 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 1656252 13250016 [ 0 1656252 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 2328116 18624928 [ 2328116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 156924 11298528 [ 0 156924 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 1753441 14027528 [ 0 96638 1656803 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 1561414 112421808 [ 1561391 23 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 94861 758888 [ 94861 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_2_Control: 156924 1255392 [ 156924 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_2_Response_Data: 79777 5743944 [ 0 79777 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_2_Response_Control: 11658 93264 [ 0 11658 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 671283 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 671283 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 671283 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 1656833 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1656833 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 79.4145% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 20.5855% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1656833 100% + + --- L1Cache --- + - Event Counts - +Load [12758313 ] 12758313 +Ifetch [145842556 ] 145842556 +Store [8926263 ] 8926263 +Inv [5226 ] 5226 +L1_Replacement [2326994 ] 2326994 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [1315735 ] 1315735 +DataS_fromL1 [0 ] 0 +Data_all_Acks [1012381 ] 1012381 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [1656252 ] 1656252 + + - Transitions - +NP Load [1315758 ] 1315758 +NP Ifetch [671193 ] 671193 +NP Store [341066 ] 341066 +NP Inv [5040 ] 5040 +NP L1_Replacement [0 ] 0 + +I Load [7 ] 7 +I Ifetch [90 ] 90 +I Store [2 ] 2 +I Inv [0 ] 0 +I L1_Replacement [87 ] 87 + +S Load [149 ] 149 +S Ifetch [145171264 ] 145171264 +S Store [0 ] 0 +S Inv [146 ] 146 +S L1_Replacement [670655 ] 670655 + +E Load [4311936 ] 4311936 +E Ifetch [0 ] 0 +E Store [158759 ] 158759 +E Inv [17 ] 17 +E L1_Replacement [1156741 ] 1156741 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 + +M Load [7130463 ] 7130463 +M Ifetch [0 ] 0 +M Store [8426436 ] 8426436 +M Inv [23 ] 23 +M L1_Replacement [499511 ] 499511 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Exclusive [1315735 ] 1315735 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [671313 ] 671313 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data [0 ] 0 +IM Data_all_Acks [341068 ] 341068 +IM Ack [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 + +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [0 ] 0 + +M_I Load [0 ] 0 +M_I Ifetch [9 ] 9 +M_I Store [0 ] 0 +M_I Inv [0 ] 0 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [1656252 ] 1656252 + +SINK_WB_ACK Load [0 ] 0 +SINK_WB_ACK Ifetch [0 ] 0 +SINK_WB_ACK Store [0 ] 0 +SINK_WB_ACK Inv [0 ] 0 +SINK_WB_ACK L1_Replacement [0 ] 0 +SINK_WB_ACK WB_Ack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 156924 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 156924 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 18.7167% + system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 9.03941% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 72.2439% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 156924 100% + + --- L2Cache --- + - Event Counts - +L1_GET_INSTR [671283 ] 671283 +L1_GETS [1315765 ] 1315765 +L1_GETX [341068 ] 341068 +L1_UPGRADE [0 ] 0 +L1_PUTX [1656252 ] 1656252 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [79764 ] 79764 +L2_Replacement_clean [11671 ] 11671 +Mem_Data [156924 ] 156924 +Mem_Ack [91435 ] 91435 +WB_Data [23 ] 23 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [5203 ] 5203 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [1656803 ] 1656803 +MEM_Inv [0 ] 0 + + - Transitions - +NP L1_GET_INSTR [14185 ] 14185 +NP L1_GETS [29371 ] 29371 +NP L1_GETX [113368 ] 113368 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 + +SS L1_GET_INSTR [656808 ] 656808 +SS L1_GETS [30 ] 30 +SS L1_GETX [530 ] 530 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [21 ] 21 +SS L2_Replacement_clean [5165 ] 5165 +SS MEM_Inv [0 ] 0 + +M L1_GET_INSTR [290 ] 290 +M L1_GETS [1286364 ] 1286364 +M L1_GETX [227170 ] 227170 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [79722 ] 79722 +M L2_Replacement_clean [6487 ] 6487 +M MEM_Inv [0 ] 0 + +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [1656252 ] 1656252 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [21 ] 21 +MT L2_Replacement_clean [19 ] 19 +MT MEM_Inv [0 ] 0 + +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [0 ] 0 +M_I L1_GETX [0 ] 0 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [91435 ] 91435 +M_I MEM_Inv [0 ] 0 + +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [10 ] 10 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [11 ] 11 +MT_I MEM_Inv [0 ] 0 + +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [13 ] 13 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [6 ] 6 + +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [5165 ] 5165 + +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [21 ] 21 +S_I MEM_Inv [0 ] 0 + +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [29371 ] 29371 +ISS MEM_Inv [0 ] 0 + +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [14185 ] 14185 +IS MEM_Inv [0 ] 0 + +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [113368 ] 113368 +IM MEM_Inv [0 ] 0 + +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [530 ] 530 +SS_MB MEM_Inv [0 ] 0 + +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [1656273 ] 1656273 +MT_MB MEM_Inv [0 ] 0 + +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 + +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 + +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 + +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 236701 + memory_reads: 156924 + memory_writes: 79777 + memory_refreshes: 3605775 + memory_total_request_delays: 22050 + memory_delays_per_request: 0.0931555 + memory_delays_in_input_queue: 3 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 22047 + memory_stalls_for_bank_busy: 9315 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 1753 + memory_stalls_for_bus: 10979 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 0 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 7384 7191 7213 7164 7259 7202 7329 7267 7403 7994 7291 7198 7274 7225 7192 6165 7120 7481 7412 7305 7478 7526 7492 7422 7552 7547 7690 7916 7923 7818 7870 7398 + + --- Directory --- + - Event Counts - +Fetch [156924 ] 156924 +Data [79777 ] 79777 +Memory_Data [156924 ] 156924 +Memory_Ack [79777 ] 79777 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [11658 ] 11658 + + - Transitions - +I Fetch [156924 ] 156924 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 + +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 + +M Data [79777 ] 79777 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [11658 ] 11658 + +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [156924 ] 156924 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 + +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [79777 ] 79777 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 + +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 + +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 + +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE [0 ] 0 + + --- DMA --- + - Event Counts - +ReadRequest [0 ] 0 +WriteRequest [0 ] 0 +Data [0 ] 0 +Ack [0 ] 0 + + - Transitions - +READY ReadRequest [0 ] 0 +READY WriteRequest [0 ] 0 + +BUSY_RD Data [0 ] 0 + +BUSY_WR Ack [0 ] 0 + diff -r 1c420a04832b -r c8bd022f464d tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr Sun Apr 08 11:34:34 2012 -0500 @@ -0,0 +1,9 @@ +warn: Sockets disabled, not accepting terminal connections +warn: Reading current count from inactive timer. +warn: Sockets disabled, not accepting gdb connections +warn: Don't know what interrupt to clear for console. +warn: instruction 'fxsave' unimplemented +warn: Tried to clear PCI interrupt 14 +warn: Unknown mouse command 0xe1. +warn: instruction 'wbinvd' unimplemented +hack: be nice to actually delete the event here diff -r 1c420a04832b -r c8bd022f464d tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout Sun Apr 08 11:34:34 2012 -0500 @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Apr 8 2012 00:59:39 +gem5 started Apr 8 2012 11:14:02 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory +warning: add_child('terminal'): child 'terminal' already has parent +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 5263950335000 because m5_exit instruction encountered diff -r 1c420a04832b -r c8bd022f464d tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt Sun Apr 08 11:34:34 2012 -0500 @@ -0,0 +1,61 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 5.263950 # Number of seconds simulated +sim_ticks 5263950335000 # Number of ticks simulated +final_tick 5263950335000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 200135 # Simulator instruction rate (inst/s) +host_op_rate 403577 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8862544296 # Simulator tick rate (ticks/s) +host_mem_usage 517600 # Number of bytes of host memory used +host_seconds 593.95 # Real time elapsed on the host +sim_insts 118870900 # Number of instructions simulated +sim_ops 239706312 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 1245063168 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1166740376 # Number of instructions bytes read from this memory +system.physmem.bytes_written 60799430 # Number of bytes written to this memory +system.physmem.num_reads 159174200 # Number of read requests responded to by this memory +system.physmem.num_writes 8400483 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 236526390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 221647299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 11550153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 248076542 # Total bandwidth to/from this memory (bytes/s) +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.numCycles 10527900670 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 118870900 # Number of instructions committed +system.cpu.committedOps 239706312 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 222114797 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 22771634 # number of instructions that are conditional controls +system.cpu.num_int_insts 222114797 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 482137885 # number of times the integer registers were read +system.cpu.num_int_register_writes 232367628 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 28055989 # number of memory refs +system.cpu.num_load_insts 19691841 # Number of load instructions +system.cpu.num_store_insts 8364148 # Number of store instructions +system.cpu.num_idle_cycles 9767295346.278145 # Number of idle cycles +system.cpu.num_busy_cycles 760605323.721855 # Number of busy cycles +system.cpu.not_idle_fraction 0.072247 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927753 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff -r 1c420a04832b -r c8bd022f464d tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal Sun Apr 08 11:34:34 2012 -0500 @@ -0,0 +1,133 @@ +Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007 +Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +BIOS-provided physical RAM map: + BIOS-e820: 0000000000000000 - 0000000000100000 (reserved) + BIOS-e820: 0000000000100000 - 0000000008000000 (usable) +end_pfn_map = 32768 +kernel direct mapping tables up to 8000000 @ 100000-102000 +DMI 2.5 present. +Zone PFN ranges: + DMA 256 -> 4096 + DMA32 4096 -> 1048576 + Normal 1048576 -> 1048576 +early_node_map[1] active PFN ranges + 0: 256 -> 32768 +Intel MultiProcessor Specification v1.4 +MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000 +Processor #0 (Bootup-CPU) +I/O APIC #1 at 0xFEC00000. +Setting APIC routing to flat +Processors: 1 +Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000) +Built 1 zonelists. Total pages: 30458 +Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +Initializing CPU#0 +PID hash table entries: 512 (order: 9, 4096 bytes) +time.c: Detected 1999.993 MHz processor. +Console: colour dummy device 80x25 +console handover: boot [earlyser0] -> real [ttyS0] +Dentry cache hash table entries: 16384 (order: 5, 131072 bytes) +Inode-cache hash table entries: 8192 (order: 4, 65536 bytes) +Checking aperture... +Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init) +Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset +Mount-cache hash table entries: 256 +CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) +CPU: L2 Cache: 1024K (64 bytes/line) +CPU: Fake M5 x86_64 CPU stepping 01 +ACPI: Core revision 20070126 +ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126] +ACPI: Unable to load the System Description Tables +Using local APIC timer interrupts. +result 7812468 +Detected 7.812 MHz APIC timer. +NET: Registered protocol family 16 +PCI: Using configuration type 1 +ACPI: Interpreter disabled. +Linux Plug and Play Support v0.97 (c) Adam Belay +pnp: PnP ACPI: disabled +SCSI subsystem initialized +usbcore: registered new interface driver usbfs +usbcore: registered new interface driver hub +usbcore: registered new device driver usb +PCI: Probing PCI hardware +PCI-GART: No AMD northbridge found. +NET: Registered protocol family 2 +Time: tsc clocksource has been installed. +IP route cache hash table entries: 1024 (order: 1, 8192 bytes) +TCP established hash table entries: 4096 (order: 4, 65536 bytes) +TCP bind hash table entries: 4096 (order: 3, 32768 bytes) +TCP: Hash tables configured (established 4096 bind 4096) +TCP reno registered +Total HugeTLB memory allocated, 0 +Installing knfsd (copyright (C) 1996 okir@monad.swb.de). +io scheduler noop registered +io scheduler deadline registered +io scheduler cfq registered (default) +Real Time Clock Driver v1.12ac +Linux agpgart interface v0.102 (c) Dave Jones +Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled +serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 +floppy0: no floppy controllers found +RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +loop: module loaded +Intel(R) PRO/1000 Network Driver - version 7.3.20-k2 +Copyright (c) 1999-2006 Intel Corporation. +e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI +e100: Copyright(c) 1999-2006 Intel Corporation +forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60. +tun: Universal TUN/TAP device driver, 1.6 +tun: (C) 1999-2004 Max Krasnyansky +netconsole: not configured, aborting +Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 +ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx +PIIX4: IDE controller at PCI slot 0000:00:04.0 +PCI: Enabling device 0000:00:04.0 (0000 -> 0001) +PIIX4: chipset revision 0 +PIIX4: not 100% native mode: will probe irqs later + ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA +hda: M5 IDE Disk, ATA DISK drive +hdb: M5 IDE Disk, ATA DISK drive +ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 +hda: max request size: 128KiB +hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33) + hda: hda1 +hdb: max request size: 128KiB +hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: unknown partition table +megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006) +megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006) +megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007 +Fusion MPT base driver 3.04.04 +Copyright (c) 1999-2007 LSI Logic Corporation +Fusion MPT SPI Host driver 3.04.04 +Fusion MPT SAS Host driver 3.04.04 +ieee1394: raw1394: /dev/raw1394 device initialized +USB Universal Host Controller Interface driver v3.0 +usbcore: registered new interface driver usblp +drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver +Initializing USB Mass Storage driver... +usbcore: registered new interface driver usb-storage +USB Mass Storage support registered. +PNP: No PS/2 controller found. Probing ports directly. +serio: i8042 KBD port at 0x60,0x64 irq 1 +serio: i8042 AUX port at 0x60,0x64 irq 12 +mice: PS/2 mouse device common for all mice +input: AT Translated Set 2 keyboard as /class/input/input0 +device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com +input: PS/2 Generic Mouse as /class/input/input1 +usbcore: registered new interface driver usbhid +drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver +oprofile: using timer interrupt. +TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 10 +IPv6 over IPv4 tunneling driver +NET: Registered protocol family 17 +EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended +VFS: Mounted root (ext2 filesystem). +Freeing unused kernel memory: 232k freed + INIT: version 2.86 booting +mounting filesystems... +loading script...