diff -r 3c76e843bd13 -r 0e8168b67024 src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh	Fri Dec 30 18:30:39 2011 -0600
+++ b/src/cpu/o3/commit.hh	Fri Dec 30 18:38:15 2011 -0600
@@ -443,6 +443,9 @@
     /** Rename map interface. */
     RenameMap *renameMap[Impl::MaxThreads];
 
+    /* Variable for keeping track if an instruction is in middle of execution */
+    bool instruction_in_flight;
+
     /** Updates commit stats based on this instruction. */
     void updateComInstStats(DynInstPtr &inst);
 
diff -r 3c76e843bd13 -r 0e8168b67024 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Fri Dec 30 18:30:39 2011 -0600
+++ b/src/cpu/o3/commit_impl.hh	Fri Dec 30 18:38:15 2011 -0600
@@ -105,7 +105,8 @@
       numThreads(params->numThreads),
       drainPending(false),
       switchedOut(false),
-      trapLatency(params->trapLatency)
+      trapLatency(params->trapLatency),
+      instruction_in_flight(false)
 {
     _status = Active;
     _nextStatus = Inactive;
@@ -717,7 +718,7 @@
 
     // Wait until all in flight instructions are finished before enterring
     // the interrupt.
-    if (cpu->instList.empty()) {
+    if (cpu->instList.empty() && (!instruction_in_flight)) {
         // Squash or record that I need to squash this cycle if
         // an interrupt needed to be handled.
         DPRINTF(Commit, "Interrupt detected.\n");
@@ -990,6 +991,8 @@
                     cpu->instDone(tid);
                 }
 
+                instruction_in_flight = !head_inst->isLastMicroop();
+
                 // Updates misc. registers.
                 head_inst->updateMiscRegs();
 
diff -r 3c76e843bd13 -r 0e8168b67024 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh	Fri Dec 30 18:30:39 2011 -0600
+++ b/src/cpu/o3/iew.hh	Fri Dec 30 18:38:15 2011 -0600
@@ -456,8 +456,6 @@
     unsigned wbCycle;
 
     /** Number of instructions in flight that will writeback. */
-
-    /** Number of instructions in flight that will writeback. */
     int wbOutstanding;
 
     /** Writeback width. */