diff -r da414ab20502 -r 1ef6680c9bbd src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Thu Aug 05 21:16:37 2010 -0700 @@ -1357,7 +1357,11 @@ action(uu_profileMiss, "\u", desc="Profile the demand miss") { peek(mandatoryQueue_in, CacheMsg) { - // profile_miss(in_msg, id); + if (L1DcacheMemory.isTagPresent(address)) { + L1DcacheMemory.profileMiss(in_msg); + } else { + L1IcacheMemory.profileMiss(in_msg); + } } } diff -r da414ab20502 -r 1ef6680c9bbd src/mem/protocol/MOESI_CMP_token-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm Thu Aug 05 21:16:37 2010 -0700 @@ -304,6 +304,17 @@ } } + GenericRequestType convertToGenericType(CoherenceRequestType type) { + if(type == CoherenceRequestType:GETS) { + return GenericRequestType:GETS; + } else if(type == CoherenceRequestType:GETX) { + return GenericRequestType:GETX; + } else { + DEBUG_EXPR(type); + error("invalid CoherenceRequestType"); + } + } + // ** OUT_PORTS ** out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache); out_port(localRequestNetwork_out, RequestMsg, L1RequestFromL2Cache); @@ -918,12 +929,13 @@ L2cacheMemory.deallocate(address); } - //action(uu_profileMiss, "\u", desc="Profile the demand miss") { - // peek(L1requestNetwork_in, RequestMsg) { - // AccessModeType not implemented - //profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, machineIDToNodeID(in_msg.Requestor)); - // } - //} + action(uu_profileMiss, "\u", desc="Profile the demand miss") { + peek(L1requestNetwork_in, RequestMsg) { + L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type), + in_msg.AccessMode, + in_msg.Prefetch); + } + } action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") { @@ -961,7 +973,7 @@ transition(NP, {L1_GETS, L1_GETX}) { a_broadcastLocalRequest; r_markNewSharer; - //uu_profileMiss; + uu_profileMiss; o_popL1RequestQueue; } @@ -1012,7 +1024,7 @@ a_broadcastLocalRequest; tt_sendLocalAckWithCollectedTokens; // send any tokens we have collected r_markNewSharer; - //uu_profileMiss; + uu_profileMiss; o_popL1RequestQueue; } @@ -1020,7 +1032,7 @@ a_broadcastLocalRequest; tt_sendLocalAckWithCollectedTokens; // send any tokens we have collected r_markNewSharer; - //uu_profileMiss; + uu_profileMiss; o_popL1RequestQueue; } @@ -1181,7 +1193,7 @@ tt_sendLocalAckWithCollectedTokens; r_markNewSharer; r_setMRU; - //uu_profileMiss; + uu_profileMiss; o_popL1RequestQueue; } @@ -1294,7 +1306,7 @@ k_dataAndAllTokensFromL2CacheToL1Requestor; r_markNewSharer; r_setMRU; - //uu_profileMiss; + uu_profileMiss; o_popL1RequestQueue; } @@ -1382,7 +1394,7 @@ transition(I_L, {L1_GETX, L1_GETS}) { a_broadcastLocalRequest; r_markNewSharer; - //uu_profileMiss; + uu_profileMiss; o_popL1RequestQueue; } @@ -1391,7 +1403,7 @@ tt_sendLocalAckWithCollectedTokens; r_markNewSharer; r_setMRU; - //uu_profileMiss; + uu_profileMiss; o_popL1RequestQueue; } diff -r da414ab20502 -r 1ef6680c9bbd src/mem/protocol/MOESI_CMP_token-msg.sm --- a/src/mem/protocol/MOESI_CMP_token-msg.sm Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/protocol/MOESI_CMP_token-msg.sm Thu Aug 05 21:16:37 2010 -0700 @@ -144,14 +144,3 @@ DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; } - -//GenericRequestType convertToGenericType(CoherenceRequestType type) { -// if(type == CoherenceRequestType:GETS) { -// return GenericRequestType:GETS; -// } else if(type == CoherenceRequestType:GETX) { -// return GenericRequestType:GETX; -// } else { -// DEBUG_EXPR(type); -// error("invalid CoherenceRequestType"); -// } -//} diff -r da414ab20502 -r 1ef6680c9bbd src/mem/protocol/RubySlicc_Profiler.sm --- a/src/mem/protocol/RubySlicc_Profiler.sm Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/protocol/RubySlicc_Profiler.sm Thu Aug 05 21:16:37 2010 -0700 @@ -40,7 +40,6 @@ void profile_L1Cache_miss(CacheMsg msg, NodeID l1cacheID); // used by CMP protocols -void profile_L2Cache_miss(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID l2cacheID); void profile_request(std::string L1CacheStateStr, std::string L2CacheStateStr, std::string directoryStateStr, std::string requestTypeStr); void profileMessageReordering(bool wasReordered); diff -r da414ab20502 -r 1ef6680c9bbd src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/protocol/RubySlicc_Types.sm Thu Aug 05 21:16:37 2010 -0700 @@ -126,6 +126,11 @@ void changePermission(Address, AccessPermission); bool isTagPresent(Address); void profileMiss(CacheMsg); + + void profileGenericRequest(GenericRequestType, + AccessModeType, + PrefetchBit); + void setMRU(Address); } diff -r da414ab20502 -r 1ef6680c9bbd src/mem/ruby/profiler/CacheProfiler.hh --- a/src/mem/ruby/profiler/CacheProfiler.hh Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/ruby/profiler/CacheProfiler.hh Thu Aug 05 21:16:37 2010 -0700 @@ -35,6 +35,7 @@ #include "mem/protocol/AccessModeType.hh" #include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Histogram.hh" @@ -49,8 +50,13 @@ void printStats(std::ostream& out) const; void clearStats(); - void addStatSample(CacheRequestType requestType, AccessModeType type, - int msgSize, PrefetchBit pfBit); + void addCacheStatSample(CacheRequestType requestType, + AccessModeType type, + PrefetchBit pfBit); + + void addGenericStatSample(GenericRequestType requestType, + AccessModeType type, + PrefetchBit pfBit); void print(std::ostream& out) const; @@ -58,9 +64,9 @@ // Private copy constructor and assignment operator CacheProfiler(const CacheProfiler& obj); CacheProfiler& operator=(const CacheProfiler& obj); + void addStatSample(AccessModeType type, PrefetchBit pfBit); std::string m_description; - Histogram m_requestSize; int64 m_misses; int64 m_demand_misses; int64 m_prefetches; @@ -68,7 +74,8 @@ int64 m_hw_prefetches; int64 m_accessModeTypeHistogram[AccessModeType_NUM]; - std::vector m_requestTypeVec; + std::vector m_cacheRequestType; + std::vector m_genericRequestType; }; inline std::ostream& diff -r da414ab20502 -r 1ef6680c9bbd src/mem/ruby/profiler/CacheProfiler.cc --- a/src/mem/ruby/profiler/CacheProfiler.cc Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/ruby/profiler/CacheProfiler.cc Thu Aug 05 21:16:37 2010 -0700 @@ -33,7 +33,7 @@ using namespace std; CacheProfiler::CacheProfiler(const string& description) - : m_requestTypeVec(int(CacheRequestType_NUM)) + : m_cacheRequestType(int(CacheRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM)) { m_description = description; @@ -60,18 +60,33 @@ int requests = 0; for (int i = 0; i < int(CacheRequestType_NUM); i++) { - requests += m_requestTypeVec[i]; + requests += m_cacheRequestType[i]; + } + + for (int i = 0; i < int(GenericRequestType_NUM); i++) { + requests += m_genericRequestType[i]; } assert(m_misses == requests); if (requests > 0) { for (int i = 0; i < int(CacheRequestType_NUM); i++) { - if (m_requestTypeVec[i] > 0) { + if (m_cacheRequestType[i] > 0) { out << description << "_request_type_" << CacheRequestType_to_string(CacheRequestType(i)) << ": " - << 100.0 * (double)m_requestTypeVec[i] / + << 100.0 * (double)m_cacheRequestType[i] / + (double)requests + << "%" << endl; + } + } + + for (int i = 0; i < int(GenericRequestType_NUM); i++) { + if (m_genericRequestType[i] > 0) { + out << description << "_request_type_" + << GenericRequestType_to_string(GenericRequestType(i)) + << ": " + << 100.0 * (double)m_genericRequestType[i] / (double)requests << "%" << endl; } @@ -90,7 +105,6 @@ } } - out << description << "_request_size: " << m_requestSize << endl; out << endl; } @@ -98,9 +112,11 @@ CacheProfiler::clearStats() { for (int i = 0; i < int(CacheRequestType_NUM); i++) { - m_requestTypeVec[i] = 0; + m_cacheRequestType[i] = 0; } - m_requestSize.clear(); + for (int i = 0; i < int(GenericRequestType_NUM); i++) { + m_genericRequestType[i] = 0; + } m_misses = 0; m_demand_misses = 0; m_prefetches = 0; @@ -112,16 +128,30 @@ } void -CacheProfiler::addStatSample(CacheRequestType requestType, - AccessModeType type, int msgSize, +CacheProfiler::addCacheStatSample(CacheRequestType requestType, + AccessModeType accessType, + PrefetchBit pfBit) +{ + m_cacheRequestType[requestType]++; + addStatSample(accessType, pfBit); +} + +void +CacheProfiler::addGenericStatSample(GenericRequestType requestType, + AccessModeType accessType, + PrefetchBit pfBit) +{ + m_genericRequestType[requestType]++; + addStatSample(accessType, pfBit); +} + +void +CacheProfiler::addStatSample(AccessModeType accessType, PrefetchBit pfBit) { m_misses++; - m_requestTypeVec[requestType]++; - - m_accessModeTypeHistogram[type]++; - m_requestSize.add(msgSize); + m_accessModeTypeHistogram[accessType]++; if (pfBit == PrefetchBit_No) { m_demand_misses++; } else if (pfBit == PrefetchBit_Yes) { diff -r da414ab20502 -r 1ef6680c9bbd src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh --- a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh Thu Aug 05 21:16:37 2010 -0700 @@ -58,8 +58,6 @@ const std::string& requestTypeStr); void profile_miss(const CacheMsg& msg, NodeID id); void profile_L1Cache_miss(const CacheMsg& msg, NodeID id); -void profile_L2Cache_miss(GenericRequestType requestType, AccessModeType type, - int msgSize, PrefetchBit pfBit, NodeID l2cacheID); void profile_token_retry(const Address& addr, AccessType type, int count); void profile_filter_action(int action); void profile_persistent_prediction(const Address& addr, AccessType type); diff -r da414ab20502 -r 1ef6680c9bbd src/mem/ruby/system/CacheMemory.hh --- a/src/mem/ruby/system/CacheMemory.hh Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/ruby/system/CacheMemory.hh Thu Aug 05 21:16:37 2010 -0700 @@ -37,6 +37,7 @@ #include "mem/protocol/AccessPermission.hh" #include "mem/protocol/CacheMsg.hh" #include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/MachineType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/DataBlock.hh" @@ -112,6 +113,10 @@ void profileMiss(const CacheMsg & msg); + void profileGenericRequest(GenericRequestType requestType, + AccessModeType accessType, + PrefetchBit pfBit); + void getMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes); void setMemoryValue(const Address& addr, char* value, diff -r da414ab20502 -r 1ef6680c9bbd src/mem/ruby/system/CacheMemory.cc --- a/src/mem/ruby/system/CacheMemory.cc Thu Aug 05 21:16:24 2010 -0700 +++ b/src/mem/ruby/system/CacheMemory.cc Thu Aug 05 21:16:37 2010 -0700 @@ -375,8 +375,19 @@ void CacheMemory::profileMiss(const CacheMsg& msg) { - m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(), - msg.getSize(), msg.getPrefetch()); + m_profiler_ptr->addCacheStatSample(msg.getType(), + msg.getAccessMode(), + msg.getPrefetch()); +} + +void +CacheMemory::profileGenericRequest(GenericRequestType requestType, + AccessModeType accessType, + PrefetchBit pfBit) +{ + m_profiler_ptr->addGenericStatSample(requestType, + accessType, + pfBit); } void