diff --git a/SConstruct b/SConstruct
--- a/SConstruct
+++ b/SConstruct
@@ -473,6 +473,7 @@
 main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
 main['SUNCC'] = CXX_V and CXX_V.find('Sun C++') >= 0
 main['ICC'] = CXX_V and CXX_V.find('Intel') >= 0
+main['CLANG'] = CXX_V and CXX_V.find('clang') >= 0
 if main['GCC'] + main['SUNCC'] + main['ICC'] > 1:
     print 'Error: How can we have two at the same time?'
     Exit(1)
@@ -501,6 +502,16 @@
     main.Append(CCFLAGS=['-library=stlport4'])
     main.Append(CCFLAGS=['-xar'])
     #main.Append(CCFLAGS=['-instances=semiexplicit'])
+elif main['CLANG']:
+    main.Append(CCFLAGS=['-pipe'])
+    main.Append(CCFLAGS=['-fno-strict-aliasing'])
+    main.Append(CCFLAGS=['-Wall', '-Wno-sign-compare', '-Wundef'])
+    main.Append(CCFLAGS=['-Wno-overloaded-virtual', '-Wno-mismatched-tags'])
+    main.Append(CCFLAGS=['-Wno-self-assign', '-Wno-tautological-compare'])
+    main.Append(CCFLAGS=['-Wno-empty-body', '-Wno-unused-function'])
+    main.Append(CCFLAGS=['-Wno-sizeof-pointer-memaccess', '-Wno-unused-label'])
+    main.Append(CXXFLAGS=['-Wno-deprecated'])
+
 else:
     print 'Error: Don\'t know what compiler options to use for your compiler.'
     print '       Please fix SConstruct and src/SConscript and try again.'
diff --git a/src/SConscript b/src/SConscript
--- a/src/SConscript
+++ b/src/SConscript
@@ -946,6 +946,11 @@
     ccflags['opt'] = '-g -O'
     ccflags['fast'] = '-fast'
     ccflags['prof'] = '-fast -g -pg'
+elif env['CLANG']:
+    ccflags['debug'] = '-ggdb3 -O0'
+    ccflags['opt'] = '-g -O3'
+    ccflags['fast'] = '-O3'
+    ccflags['prof'] = '-O3 -g -pg'
 else:
     print 'Unknown compiler, please fix compiler options'
     Exit(1)
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -132,4 +132,6 @@
 
 } // namespace AlphaISA
 
+using namespace AlphaISA;
+
 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -63,7 +63,7 @@
     : BaseTLB(p), size(p->size), nlu(0)
 {
     table = new TlbEntry[size];
-    memset(table, 0, sizeof(TlbEntry[size]));
+    memset(table, 0, sizeof(TlbEntry) * size);
     flushCache();
 }
 
@@ -279,7 +279,7 @@
 TLB::flushAll()
 {
     DPRINTF(TLB, "flushAll\n");
-    memset(table, 0, sizeof(TlbEntry[size]));
+    memset(table, 0, sizeof(TlbEntry) * size);
     flushCache();
     lookupTable.clear();
     nlu = 0;
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -46,6 +46,7 @@
 #include "arch/arm/utility.hh"
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
+#include "sim/byteswap.hh"
 
 namespace ArmISA
 {
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -107,6 +107,9 @@
     VfpRoundZero = 3
 };
 
+static inline float bitsToFp(uint64_t, float);
+static inline uint32_t fpToBits(float);
+
 template <class fpType>
 static inline bool
 flushToZero(fpType &op)
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -49,7 +49,8 @@
 
 // Basic instruction class constructor template.
 def template BasicConstructor {{
-        inline %(class_name)s::%(class_name)s(ExtMachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+        // Note: constructor should not inline
+        %(class_name)s::%(class_name)s(ExtMachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
         {
                 %(constructor)s;
                 if (!(condCode == COND_AL || condCode == COND_UC)) {
diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc
--- a/src/arch/x86/bios/intelmp.cc
+++ b/src/arch/x86/bios/intelmp.cc
@@ -78,7 +78,9 @@
     uint8_t checkSum = 0;
     while(guestVal) {
         checkSum += guestVal;
-        guestVal >>= 8;
+        // clang++ says "shift count >= width of type" on
+        // "guestVal >>= 8"
+        guestVal /= 256;
     }
     return checkSum;
 }
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -87,4 +87,6 @@
     };
 };
 
+using namespace X86ISA;
+
 #endif // __ARCH_X86_ISATRAITS_HH__
diff --git a/src/base/fast_alloc.cc b/src/base/fast_alloc.cc
--- a/src/base/fast_alloc.cc
+++ b/src/base/fast_alloc.cc
@@ -40,10 +40,6 @@
 
 #if USE_FAST_ALLOC
 
-#ifdef __GNUC__
-#pragma implementation
-#endif
-
 void *FastAlloc::freeLists[Num_Buckets];
 
 #if FAST_ALLOC_STATS
diff --git a/src/base/range_map.hh b/src/base/range_map.hh
--- a/src/base/range_map.hh
+++ b/src/base/range_map.hh
@@ -215,7 +215,7 @@
     {
         std::pair<iterator,iterator> p;
         p = find(r);
-        if (p.first->first.start == r.start && p.first->first.end == r.end ||
+        if ((p.first->first.start == r.start && p.first->first.end == r.end) ||
                 p.first == tree.end())
             return tree.insert(std::make_pair<Range<T>,V>(r, d));
         else
diff --git a/src/base/stl_helpers.hh b/src/base/stl_helpers.hh
--- a/src/base/stl_helpers.hh
+++ b/src/base/stl_helpers.hh
@@ -72,7 +72,7 @@
 
 // Treat all objects in an stl container as pointers to heap objects,
 // calling delete on each one and zeroing the pointers along the way
-template <typename T, template <typename T, typename A> class C, typename A>
+template <template <typename T, typename A> class C, typename T, typename A>
 void
 deletePointers(C<T,A> &container)
 {
@@ -81,7 +81,7 @@
 
 // Write out all elements in an stl container as a space separated
 // list enclosed in square brackets
-template <typename T, template <typename T, typename A> class C, typename A>
+template <template <typename T, typename A> class C, typename T, typename A>
 std::ostream &
 operator<<(std::ostream& out, const C<T,A> &vec)
 {
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -38,8 +38,6 @@
 #include "debug/Decode.hh"
 #include "params/DerivO3CPU.hh"
 
-using namespace std;
-
 template<class Impl>
 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
@@ -391,8 +389,8 @@
 bool
 DefaultDecode<Impl>::skidsEmpty()
 {
-    list<ThreadID>::iterator threads = activeThreads->begin();
-    list<ThreadID>::iterator end = activeThreads->end();
+    std::list<ThreadID>::iterator threads = activeThreads->begin();
+    std::list<ThreadID>::iterator end = activeThreads->end();
 
     while (threads != end) {
         ThreadID tid = *threads++;
@@ -409,8 +407,8 @@
 {
     bool any_unblocking = false;
 
-    list<ThreadID>::iterator threads = activeThreads->begin();
-    list<ThreadID>::iterator end = activeThreads->end();
+    std::list<ThreadID>::iterator threads = activeThreads->begin();
+    std::list<ThreadID>::iterator end = activeThreads->end();
 
     while (threads != end) {
         ThreadID tid = *threads++;
@@ -561,8 +559,8 @@
 
     toRenameIndex = 0;
 
-    list<ThreadID>::iterator threads = activeThreads->begin();
-    list<ThreadID>::iterator end = activeThreads->end();
+    std::list<ThreadID>::iterator threads = activeThreads->begin();
+    std::list<ThreadID>::iterator end = activeThreads->end();
 
     sortInsts();
 
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -94,9 +94,6 @@
     typedef typename CPUPol::RenameStruct RenameStruct;
     typedef typename CPUPol::IssueStruct IssueStruct;
 
-    friend class Impl::O3CPU;
-    friend class CPUPol::IQ;
-
   public:
     /** Overall IEW stage status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -93,8 +93,6 @@
     // Typedef of iterator through the list of instructions.
     typedef typename std::list<DynInstPtr>::iterator ListIt;
 
-    friend class Impl::O3CPU;
-
     /** FU completion event class. */
     class FUCompletion : public Event {
       private:
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -51,8 +51,6 @@
 #include "params/DerivO3CPU.hh"
 #include "sim/core.hh"
 
-using namespace std;
-
 template <class Impl>
 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
     int fu_idx, InstructionQueue<Impl> *iq_ptr)
@@ -414,7 +412,7 @@
 
 template <class Impl>
 void
-InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
+InstructionQueue<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
 {
     activeThreads = at_ptr;
 }
@@ -481,8 +479,8 @@
     if (iqPolicy != Dynamic || numThreads > 1) {
         int active_threads = activeThreads->size();
 
-        list<ThreadID>::iterator threads = activeThreads->begin();
-        list<ThreadID>::iterator end = activeThreads->end();
+        std::list<ThreadID>::iterator threads = activeThreads->begin();
+        std::list<ThreadID>::iterator end = activeThreads->end();
 
         while (threads != end) {
             ThreadID tid = *threads++;
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -32,10 +32,6 @@
 #include "cpu/o3/mem_dep_unit_impl.hh"
 #include "cpu/o3/store_set.hh"
 
-// Force instantation of memory dependency unit using store sets and
-// O3CPUImpl.
-template class MemDepUnit<StoreSet, O3CPUImpl>;
-
 #ifdef DEBUG
 template <>
 int
@@ -47,3 +43,7 @@
 int
 MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0;
 #endif
+
+// Force instantation of memory dependency unit using store sets and
+// O3CPUImpl.
+template class MemDepUnit<StoreSet, O3CPUImpl>;
diff --git a/src/cpu/o3/sat_counter.hh b/src/cpu/o3/sat_counter.hh
--- a/src/cpu/o3/sat_counter.hh
+++ b/src/cpu/o3/sat_counter.hh
@@ -65,7 +65,7 @@
      * @param initial_val Starting value for each counter.
      */
     SatCounter(unsigned bits, uint8_t initial_val)
-        : initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val)
+        : initialVal(initial_val), maxVal((1 << bits) - 1), counter(initial_val)
     {
         // Check to make sure initial value doesn't exceed the max
         // counter value.
diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -53,7 +53,6 @@
 #include "params/TsunamiCChip.hh"
 #include "sim/system.hh"
 
-using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc
--- a/src/dev/alpha/tsunami_io.cc
+++ b/src/dev/alpha/tsunami_io.cc
@@ -54,11 +54,10 @@
 #include "mem/port.hh"
 #include "sim/system.hh"
 
-using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
+TsunamiIO::RTC::RTC(const std::string &n, const TsunamiIOParams *p)
     : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
       tsunami(p->tsunami)
 {
@@ -251,7 +250,7 @@
 }
 
 void
-TsunamiIO::serialize(ostream &os)
+TsunamiIO::serialize(std::ostream &os)
 {
     SERIALIZE_SCALAR(rtcAddr);
     SERIALIZE_SCALAR(timerData);
@@ -268,7 +267,7 @@
 }
 
 void
-TsunamiIO::unserialize(Checkpoint *cp, const string &section)
+TsunamiIO::unserialize(Checkpoint *cp, const std::string &section)
 {
     UNSERIALIZE_SCALAR(rtcAddr);
     UNSERIALIZE_SCALAR(timerData);
diff --git a/src/dev/arm/pl111.hh b/src/dev/arm/pl111.hh
--- a/src/dev/arm/pl111.hh
+++ b/src/dev/arm/pl111.hh
@@ -53,8 +53,6 @@
 #include "params/Pl111.hh"
 #include "sim/serialize.hh"
 
-using namespace std;
-
 class Gic;
 class VncServer;
 class Bitmap;
@@ -304,7 +302,7 @@
     EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
 
     /** DMA done event */
-    vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
+    std::vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
 
     /** Wrapper to create an event out of the interrupt */
     EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -604,7 +604,7 @@
     SERIALIZE_SCALAR(fill_fifo_event_time);
     SERIALIZE_SCALAR(int_event_time);
 
-    vector<Tick> dma_done_event_tick;
+    std::vector<Tick> dma_done_event_tick;
     dma_done_event_tick.resize(maxOutstandingDma);
     for (int x = 0; x < maxOutstandingDma; x++) {
         dma_done_event_tick[x] = dmaDoneEvent[x].scheduled() ?
@@ -707,7 +707,7 @@
     if (fill_fifo_event_time)
         schedule(fillFifoEvent, fill_fifo_event_time);
 
-    vector<Tick> dma_done_event_tick;
+    std::vector<Tick> dma_done_event_tick;
     dma_done_event_tick.resize(maxOutstandingDma);
     arrayParamIn(cp, section, "dma_done_event_tick", dma_done_event_tick);
     for (int x = 0; x < maxOutstandingDma; x++) {
diff --git a/src/dev/copy_engine.cc b/src/dev/copy_engine.cc
--- a/src/dev/copy_engine.cc
+++ b/src/dev/copy_engine.cc
@@ -45,7 +45,6 @@
 #include "sim/system.hh"
 
 using namespace CopyEngineReg;
-using namespace std;
 
 CopyEngine::CopyEngine(const Params *p)
     : PciDev(p)
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -42,8 +42,6 @@
 #include "params/IdeController.hh"
 #include "sim/byteswap.hh"
 
-using namespace std;
-
 // Bus master IDE registers
 enum BMIRegOffset {
     BMICommand = 0x0,
@@ -64,7 +62,7 @@
 static const uint16_t timeRegWithDecodeEn = 0x8000;
 
 IdeController::Channel::Channel(
-        string newName, Addr _cmdSize, Addr _ctrlSize) :
+        std::string newName, Addr _cmdSize, Addr _ctrlSize) :
     _name(newName),
     cmdAddr(0), cmdSize(_cmdSize), ctrlAddr(0), ctrlSize(_ctrlSize),
     master(NULL), slave(NULL), selected(NULL)
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -81,7 +81,6 @@
     "dmaWriteWaiting"
 };
 
-using namespace std;
 using namespace Net;
 using namespace TheISA;
 
@@ -1804,7 +1803,7 @@
                  * is not enough room in the fifo, just whatever room
                  * is left in the fifo
                  */
-                txXferLen = min<uint32_t>(txDescCnt, txFifo.avail());
+                txXferLen = std::min<uint32_t>(txDescCnt, txFifo.avail());
 
                 txDmaAddr = txFragPtr & 0x3fffffff;
                 txDmaData = txPacketBufPtr;
@@ -2010,7 +2009,7 @@
 {
     EthPtr eth = packet;
     bool drop = true;
-    string type;
+    std::string type;
 
     const EthAddr &dst = eth->dst();
     if (dst.unicast()) {
@@ -2115,7 +2114,7 @@
 //
 //
 void
-NSGigE::serialize(ostream &os)
+NSGigE::serialize(std::ostream &os)
 {
     // Serialize the PciDev base class
     PciDev::serialize(os);
diff --git a/src/dev/pciconfigall.cc b/src/dev/pciconfigall.cc
--- a/src/dev/pciconfigall.cc
+++ b/src/dev/pciconfigall.cc
@@ -43,8 +43,6 @@
 #include "params/PciConfigAll.hh"
 #include "sim/system.hh"
 
-using namespace std;
-
 PciConfigAll::PciConfigAll(const Params *p)
     : PioDevice(p)
 {
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -52,8 +52,6 @@
 #include "sim/byteswap.hh"
 #include "sim/core.hh"
 
-using namespace std;
-
 
 PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
         int funcid, Platform *p)
@@ -340,7 +338,7 @@
 }
 
 void
-PciDev::serialize(ostream &os)
+PciDev::serialize(std::ostream &os)
 {
     SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
     SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -73,6 +73,7 @@
         MSHRQueue_WriteBuffer
     };
 
+  public:
     /**
      * Reasons for caches to be blocked.
      */
@@ -83,7 +84,6 @@
         NUM_BLOCKED_CAUSES
     };
 
-  public:
     /**
      * Reasons for cache to request a bus.
      */
@@ -94,8 +94,6 @@
         NUM_REQUEST_CAUSES
     };
 
-  private:
-
     class CachePort : public SimpleTimingPort
     {
       public: