diff -r f348cf78072c configs/common/FSConfig.py
--- a/configs/common/FSConfig.py	Thu Jan 12 10:15:00 2012 -0500
+++ b/configs/common/FSConfig.py	Fri Jan 13 03:22:43 2012 +0800
@@ -267,11 +267,6 @@
 
 
 def makeLinuxMipsSystem(mem_mode, mdesc = None):
-    class BaseMalta(Malta):
-        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
-        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
-                            pci_func=0, pci_dev=0, pci_bus=0)
-
     self = LinuxMipsSystem()
     if not mdesc:
         # generic system
@@ -280,26 +275,19 @@
     self.iobus = Bus(bus_id=0)
     self.membus = MemBus(bus_id=1)
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
-    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
+    self.physmem = PhysicalMemory(range = AddrRange(Addr('64MB')), zero = True)
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
     self.physmem.port = self.membus.port
-    self.disk0 = CowIdeDisk(driveID='master')
-    self.disk2 = CowIdeDisk(driveID='master')
-    self.disk0.childImage(mdesc.disk())
-    self.disk2.childImage(disk('linux-bigswap2.img'))
-    self.malta = BaseMalta()
-    self.malta.attachIO(self.iobus)
-    self.malta.ide.pio = self.iobus.port
-    self.malta.ethernet.pio = self.iobus.port
-    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
-                                               read_only = True))
+
+    self.realview = RealViewPBX()
+    self.realview.attachOnChipIO(self.membus)
+    self.realview.attachIO(self.iobus)
     self.intrctrl = IntrControl()
     self.mem_mode = mem_mode
     self.terminal = Terminal()
-    self.kernel = binary('mips/vmlinux')
-    self.console = binary('mips/console')
-    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+    self.kernel = binary('vmlinux.mips')
+    self.boot_osflags = 'console=ttyAMA0 lpj=19988480'
 
     return self
 
diff -r f348cf78072c configs/example/fs.py
--- a/configs/example/fs.py	Thu Jan 12 10:15:00 2012 -0500
+++ b/configs/example/fs.py	Fri Jan 13 03:22:43 2012 +0800
@@ -179,8 +179,8 @@
     if options.fastmem:
         test_sys.cpu[i].physmem_port = test_sys.physmem.port
 
-if buildEnv['TARGET_ISA'] == 'mips':
-    setMipsOptions(TestCPUClass)
+#if buildEnv['TARGET_ISA'] == 'mips':
+#    setMipsOptions(TestCPUClass)
 
 if len(bm) == 2:
     if buildEnv['TARGET_ISA'] == 'alpha':
diff -r f348cf78072c src/arch/mips/MipsSystem.py
--- a/src/arch/mips/MipsSystem.py	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/MipsSystem.py	Fri Jan 13 03:22:43 2012 +0800
@@ -28,31 +28,25 @@
 #
 # Authors: Jaidev Patwardhan
 
-from m5.defines import buildEnv
 from m5.params import *
-from m5.proxy import *
 
 from System import System
 
 class MipsSystem(System):
     type = 'MipsSystem'
-    console = Param.String("file that contains the console code")
-    bare_iron = Param.Bool(False, "Using Bare Iron Mode?")
-    hex_file_name = Param.String("test.hex","hex file that contains [address,data] pairs")
-    system_type = Param.UInt64("Type of system we are emulating")
-    system_rev = Param.UInt64("Revision of system we are emulating")
-    load_addr_mask = 0xffffffffff
+    load_addr_mask = 0xffffffff
+    # 0x35 Implementor is '5' from "M5"
+    # 0x0 Variant
+    # 0xf Architecture from CPUID scheme
+    # 0xf00 Primary part number
+    # 0x0 Revision
+    midr_regval = Param.UInt32(0x350ff000, "MIDR value")
+    boot_loader = Param.String("", "File that contains the boot loader code if any")
+    boot_loader_mem = Param.PhysicalMemory(NULL,
+                          "Memory object that boot loader is to be loaded into")
+    gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
+    flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
 
-if buildEnv['FULL_SYSTEM']:
-    class LinuxMipsSystem(MipsSystem):
-        type = 'LinuxMipsSystem'
-        system_type = 34
-        system_rev = 1 << 10
-
-    class BareIronMipsSystem(MipsSystem):
-        type = 'BareIronMipsSystem'
-        bare_iron = True
-        system_type = 34
-        system_rev = 1 << 10
-        hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
-
+class LinuxMipsSystem(MipsSystem):
+    type = 'LinuxMipsSystem'
+    load_addr_mask = 0x1fffffff
diff -r f348cf78072c src/arch/mips/SConscript
--- a/src/arch/mips/SConscript	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/SConscript	Fri Jan 13 03:22:43 2012 +0800
@@ -54,7 +54,7 @@
         Source('stacktrace.cc')
         Source('linux/system.cc')
         Source('interrupts.cc')
-        Source('bare_iron/system.cc')
+        #Source('bare_iron/system.cc')
     else:
         Source('process.cc')
         Source('linux/linux.cc')
diff -r f348cf78072c src/arch/mips/interrupts.hh
--- a/src/arch/mips/interrupts.hh	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/interrupts.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -46,9 +46,24 @@
 namespace MipsISA
 {
 
+enum InterruptTypes
+{
+    IT_SOFT_INT0,
+    IT_SOFT_INT1,
+    IT_HARD_INT0,
+    IT_HARD_INT1,
+    IT_HARD_INT2,
+    IT_HARD_INT3,
+    IT_HARD_INT4,
+    IT_HARD_INT5,
+    NumInterruptTypes
+};
+
 class Interrupts : public SimObject
 {
   public:
+    uint8_t intVector;
+
     typedef MipsInterruptsParams Params;
 
     const Params *
diff -r f348cf78072c src/arch/mips/interrupts.cc
--- a/src/arch/mips/interrupts.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/interrupts.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -36,6 +36,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
 
 namespace MipsISA
 {
@@ -68,14 +69,22 @@
 void
 Interrupts::post(int int_num, int index)
 {
-    fatal("Must use Thread Context when posting MIPS Interrupts in M5");
+    DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
+
+    if (int_num < 0 || int_num >= NumInterruptTypes)
+        panic("int_num out of bounds\n");
+
+    if (index != 0)
+        panic("No support for other interrupt indexes\n");
+
+    intVector |= 1 << int_num;
 }
 
 void
 Interrupts::clear(int int_num, ThreadContext* tc)
 {
     DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
-    if (int_num < 0 || int_num >= NumInterruptLevels)
+    if (int_num < 0 || int_num >= NumInterruptTypes)
         panic("int_num out of bounds\n");
 
     uint8_t intstatus = getCauseIP(tc);
@@ -86,7 +95,15 @@
 void
 Interrupts::clear(int int_num, int index)
 {
-    fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
+    DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
+
+    if (int_num < 0 || int_num >= NumInterruptTypes)
+        panic("int_num out of bounds\n");
+
+    if (index != 0)
+        panic("No support for other interrupt indexes\n");
+
+    intVector &= ~((1) << int_num);
 }
 
 void
@@ -100,7 +117,8 @@
 void
 Interrupts::clearAll()
 {
-    fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
+    DPRINTF(Interrupt, "Interrupts all cleared\n");
+    intVector = 0;
 }
 
 
@@ -119,7 +137,7 @@
         // So if any interrupt that isn't masked is detected, jump to interrupt
         // handler
         CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
-        if (status.im && cause.ip) {
+        if (status.im & cause.ip) {
             DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
                     (unsigned)status.im, (unsigned)cause.ip);
             return new InterruptFault;
@@ -148,19 +166,18 @@
 bool
 Interrupts::interruptsPending(ThreadContext *tc) const
 {
-    //if there is a on cpu timer interrupt (i.e. Compare == Count)
-    //update CauseIP before proceeding to interrupt
-    if (onCpuTimerInterrupt(tc)) {
-        DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
-        //determine timer interrupt IP #
-        IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
-        uint8_t intStatus = getCauseIP(tc);
-        intStatus |= 1 << intCtl.ipti;
-        setCauseIP(tc, intStatus);
+    if (!intVector)
+        return false;
+
+    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
+    if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
+        uint8_t intstatus = getCauseIP(tc);
+        intstatus |= intVector;
+        setCauseIP(tc, intstatus);
+        return intVector;
+    } else {
+        return false;
     }
-
-    return (getCauseIP(tc) != 0);
-
 }
 
 }
diff -r f348cf78072c src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/isa.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -152,6 +152,8 @@
         for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
             miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
     }
+
+    configCP();
 }
 
 
@@ -162,9 +164,67 @@
             numThreads, numVpes);
 
     CoreSpecific cp;
-    panic("CP state must be set before the following code is used");
 
     // Do Default CP0 initialization HERE
+    // Move here from FSConfig.py --zxli
+    // 1. CP0 Configuration
+    cp.CP0_PRId_CompanyOptions = 0;
+    cp.CP0_PRId_CompanyID = 1;
+    cp.CP0_PRId_ProcessorID = 147;
+    cp.CP0_PRId_Revision = 0;
+
+    // 2. CP0 Interrupt Control
+    cp.CP0_IntCtl_IPTI = 7;
+    cp.CP0_IntCtl_IPPCI = 7;
+
+    // 3. Config Register
+    //cp.CP0_Config_K23 = 0 # Since TLB
+    //cp.CP0_Config_KU = 0 # Since TLB
+    cp.CP0_Config_BE = 0; // Little Endian
+    cp.CP0_Config_AR = 1; // Architecture Revision 2
+    cp.CP0_Config_AT = 0; // MIPS32
+    cp.CP0_Config_MT = 1; // TLB MMU
+    //cp.CP0_Config_K0 = 2; // Uncached
+
+    // 4. Config 1 Register
+    cp.CP0_Config1_M = 1; // Config2 Implemented
+    cp.CP0_Config1_MMU = 63; // TLB Size
+    // ***VERY IMPORTANT***
+    // Remember to modify CP0_Config1 according to cache specs
+    // Examine file ../common/Cache.py
+    cp.CP0_Config1_IS = 1; // I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
+    cp.CP0_Config1_IL = 5; // I-Cache Line Size, default in Cache.py is 64, i.e 5
+    cp.CP0_Config1_IA = 1; // I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
+    cp.CP0_Config1_DS = 2; // D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
+    cp.CP0_Config1_DL = 5; // D-Cache Line Size, default is 64, i.e., 5
+    cp.CP0_Config1_DA = 1; // D-Cache Associativity, default is 2, i.e. 1
+    cp.CP0_Config1_C2 = 0; // Coprocessor 2 not implemented(?)
+    cp.CP0_Config1_MD = 0; // MDMX ASE not implemented in Mips32
+    cp.CP0_Config1_PC = 1; // Performance Counters Implemented
+    cp.CP0_Config1_WR = 0; // Watch Registers Implemented
+    cp.CP0_Config1_CA = 0; // Mips16e NOT implemented
+    cp.CP0_Config1_EP = 0; // EJTag Not Implemented
+    cp.CP0_Config1_FP = 0; // FPU Implemented
+
+    // 5. Config 2 Register
+    cp.CP0_Config2_M =  1; //Config3 Implemented
+    cp.CP0_Config2_TU = 0; //Tertiary Cache Control
+    cp.CP0_Config2_TS = 0; //Tertiary Cache Sets Per Way
+    cp.CP0_Config2_TL = 0; //Tertiary Cache Line Size
+    cp.CP0_Config2_TA = 0; //Tertiary Cache Associativity
+    cp.CP0_Config2_SU = 0; //Secondary Cache Control
+    cp.CP0_Config2_SS = 0; //Secondary Cache Sets Per Way
+    cp.CP0_Config2_SL = 0; //Secondary Cache Line Size
+    cp.CP0_Config2_SA = 0; //Secondary Cache Associativity
+
+    // 6. Config 3 Register
+    cp.CP0_Config3_M = 0;    //Config4 Not Implemented
+    cp.CP0_Config3_DSPP = 1; //DSP ASE Present
+    cp.CP0_Config3_LPA = 0;  //Large Physical Addresses Not supported in Mips32
+    cp.CP0_Config3_VEIC = 0; //EIC Supported
+    cp.CP0_Config3_VInt = 0; //Vectored Interrupts Implemented
+    cp.CP0_Config3_SP = 0;   //Small Pages Supported (PageGrain reg. exists)
+	
 
     // Do Initialization for MT cores here (eventually use
     // core_name parameter to toggle this initialization)
diff -r f348cf78072c src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/isa/decoder.isa	Fri Jan 13 03:22:43 2012 +0800
@@ -649,7 +649,8 @@
                         StatusReg status = Status;
                         ConfigReg config = Config;
                         SRSCtlReg srsCtl = SRSCtl;
-                        DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
+                        // TODO: here met a compiling error: NPC may be used uninitialized
+                        DPRINTF(MipsPRA,"Restoring PC - %x, NPC=%x, NNPC=%x\n",EPC, NPC, NNPC);
                         if (status.erl == 1) {
                             status.erl = 0;
                             NPC = ErrorEPC;
@@ -777,6 +778,9 @@
                             SP = 1;
                         }
                         Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
+                        // Add here for unify the ITB and DTB --zxli
+                        Ptr = xc->tcBase()->getDTBPtr();
+                        Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
                     }});
                     0x06: tlbwr({{
                         //Create PTE
@@ -841,7 +845,14 @@
                             bits(pageGrain, pageGrain.esp) == 1) {
                             SP = 1;
                         }
-                        Ptr->insertAt(newEntry, Random, SP);
+
+                        // TODO: generate a real random number here
+                        static int random = 0;
+                        random = (random + 1) % 64;
+                        Ptr->insertAt(newEntry, random, SP);
+                        // Add here for unify the ITB and DTB --zxli
+                        Ptr = xc->tcBase()->getDTBPtr();
+                        Ptr->insertAt(newEntry, random, SP);
                     }});
 
                     0x08: tlbp({{
@@ -867,9 +878,10 @@
                         }
                     }});
                 }
-                format CP0Unimpl {
-                    0x20: wait();
-                }
+                0x20: BasicOp::wait({{
+                    // TODO: check the function of wait instruction
+                    //fault = new CoprocessorUnusableFault(0);
+                }}, IsMemBarrier);
                 default: CP0Unimpl::unknown();
             }
         }
@@ -2430,11 +2442,14 @@
                         }
                     }
                 }
-                0x3: decode OP default FailUnimpl::rdhwr() {
+                0x3: decode OP {
                     0x0: decode FULL_SYSTEM {
                         0: decode RD {
                             29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
                         }
+                        1: CP0Control::rdhwr({{
+                            fault = new CoprocessorUnusableFault(0);
+                        }});
                     }
                 }
             }
diff -r f348cf78072c src/arch/mips/linux/system.hh
--- a/src/arch/mips/linux/system.hh	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/linux/system.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -33,105 +33,50 @@
 #ifndef __ARCH_MIPS_LINUX_SYSTEM_HH__
 #define __ARCH_MIPS_LINUX_SYSTEM_HH__
 
-class ThreadContext;
+#include <string>
+#include <vector>
 
-class BreakPCEvent;
-class IdleStartEvent;
-
-#include "arch/mips/idle_event.hh"
 #include "arch/mips/system.hh"
 #include "kern/linux/events.hh"
 #include "params/LinuxMipsSystem.hh"
 
-/**
- * This class contains linux specific system code (Loading, Events).
- * It points to objects that are the system binaries to load and patches them
- * appropriately to work in simulator.
- */
 class LinuxMipsSystem : public MipsSystem
 {
-  private:
-    class SkipDelayLoopEvent : public SkipFuncEvent
-    {
-      public:
-        SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr)
-            : SkipFuncEvent(q, desc, addr) {}
-        virtual void process(ThreadContext *tc);
-    };
-
-    class PrintThreadInfo : public PCEvent
-    {
-      public:
-        PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr)
-            : PCEvent(q, desc, addr) {}
-        virtual void process(ThreadContext *tc);
-    };
-
-
-    /**
-     * Addresses defining where the kernel bootloader places various
-     * elements.  Details found in include/asm-mips/system.h
-     */
-    Addr KernelStart; // Lookup the symbol swapper_pg_dir
+  protected:
+    static const int ParamsList =  0x100;
 
   public:
-    Addr InitStack() const { return KernelStart + 0x02000; }
-    Addr EmptyPGT() const  { return KernelStart + 0x04000; }
-    Addr EmptyPGE() const  { return KernelStart + 0x08000; }
-    Addr ZeroPGE() const   { return KernelStart + 0x0A000; }
-    Addr StartAddr() const { return KernelStart + 0x10000; }
+    /** Boilerplate params code */
+    typedef LinuxMipsSystemParams Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
-    Addr Param() const { return ZeroPGE() + 0x0; }
-    Addr CommandLine() const { return Param() + 0x0; }
-    Addr InitrdStart() const { return Param() + 0x100; }
-    Addr InitrdSize() const { return Param() + 0x108; }
-    static const int CommandLineSize = 256;
+    LinuxMipsSystem(Params *p);
+    ~LinuxMipsSystem();
+
+    void initState();
 
   private:
 #ifndef NDEBUG
     /** Event to halt the simulator if the kernel calls panic()  */
     BreakPCEvent *kernelPanicEvent;
+#endif
+    /**
+     * PC based event to skip udelay(<time>) calls and quiesce the
+     * processor for the appropriate amount of time. This is not functionally
+     * required but does speed up simulation.
+     */
+    Linux::UDelayEvent *uDelaySkipEvent;
 
-    /** Event to halt the simulator if the kernel calls die_if_kernel  */
-    BreakPCEvent *kernelDieEvent;
-#endif
-
-    /**
-     * Event to skip determine_cpu_caches() because we don't support
-     * the IPRs that the code can access to figure out cache sizes
+    /** Another PC based skip event for const_udelay(). Similar to the udelay
+     * skip, but this function precomputes the first multiply that is done
+     * in the generic case since the parameter is known at compile time.
+     * Thus we need to do some division to get back to us.
      */
-    SkipFuncEvent *skipCacheProbeEvent;
-
-    /** PC based event to skip the ide_delay_50ms() call */
-    SkipFuncEvent *skipIdeDelay50msEvent;
-
-    /**
-     * PC based event to skip the dprink() call and emulate its
-     * functionality
-     */
-    Linux::DebugPrintkEvent *debugPrintkEvent;
-
-    /**
-     * Skip calculate_delay_loop() rather than waiting for this to be
-     * calculated
-     */
-    SkipDelayLoopEvent *skipDelayLoopEvent;
-
-    /**
-     * Event to print information about thread switches if the trace flag
-     * Thread is set
-     */
-    PrintThreadInfo *printThreadEvent;
-
-    /** Grab the PCBB of the idle process when it starts */
-    IdleStartEvent *idleStartEvent;
-
-  public:
-    typedef LinuxMipsSystemParams Params;
-    LinuxMipsSystem(Params *p);
-    ~LinuxMipsSystem();
-
-    void setDelayLoop(ThreadContext *tc);
+    Linux::UDelayEvent *constUDelaySkipEvent;
 };
 
 #endif // __ARCH_MIPS_LINUX_SYSTEM_HH__
diff -r f348cf78072c src/arch/mips/linux/system.cc
--- a/src/arch/mips/linux/system.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/linux/system.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -30,156 +30,41 @@
  *          Nathan Binkert
  */
 
-/**
- * @file
- * This code loads the linux kernel, console, pal and patches certain
- * functions.  The symbol tables are loaded so that traces can show
- * the executing function and we can skip functions. Various delay
- * loops are skipped and their final values manually computed to speed
- * up boot time.
- */
+#include "arch/mips/linux/system.hh"
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
+#include "base/loader/object_file.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
+#include "kern/linux/events.hh"
+#include "mem/physical.hh"
 
-#include "arch/mips/linux/system.hh"
-#include "arch/mips/linux/threadinfo.hh"
-#include "arch/mips/idle_event.hh"
-#include "arch/mips/system.hh"
-#include "arch/vtophys.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-#include "dev/platform.hh"
-#include "kern/linux/events.hh"
-#include "kern/linux/printk.hh"
-#include "mem/physical.hh"
-#include "mem/port.hh"
-#include "sim/arguments.hh"
-#include "sim/byteswap.hh"
-
-using namespace std;
 using namespace MipsISA;
 using namespace Linux;
 
 LinuxMipsSystem::LinuxMipsSystem(Params *p)
     : MipsSystem(p)
 {
-    Addr addr = 0;
+    // Load symbols at physical address, we might not want
+    // to do this perminately, for but early bootup work
+    // it is helpfulp.
+    kernel->loadGlobalSymbols(kernelSymtab, loadAddrMask);
+    kernel->loadGlobalSymbols(debugSymbolTable, loadAddrMask);
+}
 
-    /**
-     * The symbol swapper_pg_dir marks the beginning of the kernel and
-     * the location of bootloader passed arguments
-     */
-    if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) {
-        panic("Could not determine start location of kernel");
-    }
-
-    /**
-     * Since we aren't using a bootloader, we have to copy the
-     * kernel arguments directly into the kernel's memory.
-     */
-    virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
-                params()->boot_osflags.length()+1);
-
-    /**
-     * find the address of the est_cycle_freq variable and insert it
-     * so we don't through the lengthly process of trying to
-     * calculated it by using the PIT, RTC, etc.
-     */
-    if (kernelSymtab->findAddress("est_cycle_freq", addr))
-        virtPort.write(addr, (uint64_t)(SimClock::Frequency /
-                    p->boot_cpu_frequency));
-
-    /**
-     * EV5 only supports 127 ASNs so we are going to tell the kernel that the
-     * paritiuclar EV6 we have only supports 127 asns.
-     * @todo At some point we should change ev5.hh and the palcode to support
-     * 255 ASNs.
-     */
-    if (kernelSymtab->findAddress("dp264_mv", addr))
-        virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
-    else
-        panic("could not find dp264_mv\n");
-
-#ifndef NDEBUG
-    kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic");
-    if (!kernelPanicEvent)
-        panic("could not find kernel symbol \'panic\'");
-
-#endif
-
-    /**
-     * Any time ide_delay_50ms, calibarte_delay or
-     * determine_cpu_caches is called just skip the
-     * function. Currently determine_cpu_caches only is used put
-     * information in proc, however if that changes in the future we
-     * will have to fill in the cache size variables appropriately.
-     */
-
-    skipIdeDelay50msEvent =
-        addKernelFuncEvent<SkipFuncEvent>("ide_delay_50ms");
-    skipDelayLoopEvent =
-        addKernelFuncEvent<SkipDelayLoopEvent>("calibrate_delay");
-    skipCacheProbeEvent =
-        addKernelFuncEvent<SkipFuncEvent>("determine_cpu_caches");
-    debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
-    idleStartEvent = addKernelFuncEvent<IdleStartEvent>("cpu_idle");
-
-    // Disable for now as it runs into panic() calls in VPTr methods
-    // (see sim/vptr.hh).  Once those bugs are fixed, we can
-    // re-enable, but we should find a better way to turn it on than
-    // using DTRACE(Thread), since looking at a trace flag at tick 0
-    // leads to non-intuitive behavior with --trace-start.
-    if (false && kernelSymtab->findAddress("mips_switch_to", addr)) {
-        printThreadEvent = new PrintThreadInfo(&pcEventQueue, "threadinfo",
-                                               addr + sizeof(MachInst) * 6);
-    } else {
-        printThreadEvent = NULL;
-    }
+void
+LinuxMipsSystem::initState()
+{
+    MipsSystem::initState();
 }
 
 LinuxMipsSystem::~LinuxMipsSystem()
 {
-#ifndef NDEBUG
-    delete kernelPanicEvent;
-#endif
-    delete skipIdeDelay50msEvent;
-    delete skipDelayLoopEvent;
-    delete skipCacheProbeEvent;
-    delete debugPrintkEvent;
-    delete idleStartEvent;
-    delete printThreadEvent;
-}
-
-
-void
-LinuxMipsSystem::setDelayLoop(ThreadContext *tc)
-{
-    Addr addr = 0;
-    if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
-        Tick cpuFreq = tc->getCpuPtr()->frequency();
-        Tick intrFreq = platform->intrFrequency();
-        VirtualPort *vp;
-
-        vp = tc->getVirtPort();
-        vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
-    }
-}
-
-
-void
-LinuxMipsSystem::SkipDelayLoopEvent::process(ThreadContext *tc)
-{
-    SkipFuncEvent::process(tc);
-    // calculate and set loops_per_jiffy
-    ((LinuxMipsSystem *)tc->getSystemPtr())->setDelayLoop(tc);
-}
-
-void
-LinuxMipsSystem::PrintThreadInfo::process(ThreadContext *tc)
-{
-    Linux::ThreadInfo ti(tc);
-
-    DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n",
-            ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
+    if (uDelaySkipEvent)
+        delete uDelaySkipEvent;
+    if (constUDelaySkipEvent)
+        delete constUDelaySkipEvent;
 }
 
 LinuxMipsSystem *
diff -r f348cf78072c src/arch/mips/locked_mem.hh
--- a/src/arch/mips/locked_mem.hh	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/locked_mem.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -50,8 +50,8 @@
 inline void
 handleLockedRead(XC *xc, Request *req)
 {
-    xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
-    xc->setMiscReg(MISCREG_LLFLAG, true);
+    xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf);
+    xc->setMiscRegNoEffect(MISCREG_LLFLAG, true);
     DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
                   " Address set to %x.\n",
             req->threadId(), req->getPaddr() & ~0xf);
@@ -74,7 +74,7 @@
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
             req->setExtraData(0);
-            xc->setMiscReg(MISCREG_LLFLAG, false);
+            xc->setMiscRegNoEffect(MISCREG_LLFLAG, false);
 
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect
diff -r f348cf78072c src/arch/mips/remote_gdb.cc
--- a/src/arch/mips/remote_gdb.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/remote_gdb.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -133,8 +133,6 @@
 #include <sys/signal.h>
 #include <unistd.h>
 
-#include <string>
-
 #include "arch/mips/remote_gdb.hh"
 #include "arch/mips/vtophys.hh"
 #include "config/full_system.hh"
@@ -144,7 +142,6 @@
 #include "debug/GDBMisc.hh"
 #include "mem/page_table.hh"
 
-using namespace std;
 using namespace MipsISA;
 
 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
@@ -159,12 +156,25 @@
 RemoteGDB::acc(Addr va, size_t len)
 {
 #if FULL_SYSTEM
-    panic("acc not implemented for MIPS FS!");
-#endif
+    Addr last_va;
+    va = TruncPage(va);
+    last_va = RoundPage(va + len);
+
+    do {
+        if (vtophys(va) != -1) {
+            return true;
+        }
+        va += PageBytes;
+    } while (va < last_va);
+
+    DPRINTF(GDBAcc, "acc:   %#x mapping is valid\n", va);
+    return true;
+#else
     TlbEntry entry;
     //Check to make sure the first byte is mapped into the processes address
     //space.
     return context->getProcessPtr()->pTable->lookup(va, entry);
+#endif
 }
 
 /*
diff -r f348cf78072c src/arch/mips/stacktrace.cc
--- a/src/arch/mips/stacktrace.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/stacktrace.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -37,6 +37,7 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "mem/vport.hh"
 #include "sim/system.hh"
 
 using namespace std;
diff -r f348cf78072c src/arch/mips/system.hh
--- a/src/arch/mips/system.hh	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/system.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -37,67 +37,43 @@
 #include <string>
 #include <vector>
 
-#include "base/loader/hex_file.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/pc_event.hh"
-#include "kern/system_events.hh"
+#include "kern/linux/events.hh"
 #include "params/MipsSystem.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
 class MipsSystem : public System
 {
+  protected:
+    /**
+     * PC based event to skip the dprink() call and emulate its
+     * functionality
+     */
+    Linux::DebugPrintkEvent *debugPrintkEvent;
+
+    /**
+     * Pointer to the bootloader object
+     */
+    ObjectFile *bootldr;
+
   public:
     typedef MipsSystemParams Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
     MipsSystem(Params *p);
     ~MipsSystem();
 
-    virtual bool breakpoint();
+    void initState();
 
-  public:
-    /**
-     * Serialization stuff
-     */
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-    /**
-     * Set the m5MipsAccess pointer in the console
-     */
-    void setMipsAccess(Addr access);
-
-#if FULL_SYSTEM
-    /** console symbol table */
-    SymbolTable *consoleSymtab;
-
-    /** Object pointer for the console code */
-    ObjectFile *console;
-
-    /** Used by some Bare Iron Configurations */
-    HexFile *hexFile;
-#endif
-
-#ifndef NDEBUG
-  /** Event to halt the simulator if the console calls panic() */
-    BreakPCEvent *consolePanicEvent;
-#endif
-
-  protected:
-    const Params *params() const { return (const Params *)_params; }
-
-
-#if FULL_SYSTEM
-  /** Add a function-based event to the console code. */
-    template <class T>
-    T *
-    addConsoleFuncEvent(const char *lbl)
+    virtual Addr fixFuncEventAddr(Addr addr)
     {
-        return addFuncEvent<T>(consoleSymtab, lbl);
+        return addr;
     }
 
-    virtual Addr fixFuncEventAddr(Addr addr);
-#endif
-
 };
 
 #endif
diff -r f348cf78072c src/arch/mips/system.cc
--- a/src/arch/mips/system.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/system.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -32,120 +32,63 @@
  */
 
 #include "arch/mips/system.hh"
-#include "arch/vtophys.hh"
-#include "base/loader/hex_file.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
-#include "base/trace.hh"
+#include "cpu/thread_context.hh"
 #include "mem/physical.hh"
-#include "params/MipsSystem.hh"
-#include "sim/byteswap.hh"
 
-using namespace LittleEndianGuest;
+using namespace Linux;
 
-MipsSystem::MipsSystem(Params *p) : System(p)
+MipsSystem::MipsSystem(Params *p)
+    : System(p), bootldr(NULL)
 {
+    debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
 
-#if FULL_SYSTEM
-    if (p->bare_iron == true) {
-        hexFile = new HexFile(params()->hex_file_name);
-        if (!hexFile->loadSections(functionalPort))
-            panic("Could not load hex file\n");
+    if ((p->boot_loader == "") != (p->boot_loader_mem == NULL))
+        fatal("If boot_loader is specifed, memory to load it must be also.\n");
+
+    if (p->boot_loader != "") {
+        bootldr = createObjectFile(p->boot_loader);
+
+        if (!bootldr)
+            fatal("Could not read bootloader: %s\n", p->boot_loader);
+
+        Port *mem_port;
+        FunctionalPort fp(name() + "-fport");
+        mem_port = p->boot_loader_mem->getPort("functional");
+        fp.setPeer(mem_port);
+        mem_port->setPeer(&fp);
+
+        bootldr->loadSections(&fp);
+        bootldr->loadGlobalSymbols(debugSymbolTable);
+
+        uint8_t jump_to_bl[] =
+        {
+            0x07, 0xf0, 0xa0, 0xe1  // branch to r7
+        };
+        functionalPort->writeBlob(0x0, jump_to_bl, sizeof(jump_to_bl));
     }
+}
 
-    Addr addr = 0;
-
-    consoleSymtab = new SymbolTable;
-
-
-    /**
-     * Load the console code into memory
-     */
-    //    Load Console Code
-    console = createObjectFile(params()->console);
-
-    warn("console code is located at: %s\n", params()->console);
-
-    if (console == NULL)
-        fatal("Could not load console file %s", params()->console);
-    //Load program sections into memory
-    console->loadSections(functionalPort, loadAddrMask);
-
-    //load symbols
-    if (!console->loadGlobalSymbols(consoleSymtab))
-        panic("could not load console symbols\n");
-
-    if (!console->loadGlobalSymbols(debugSymbolTable))
-        panic("could not load console symbols\n");
-
-
-#ifndef NDEBUG
-    consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic");
-#endif
-
-    /**
-     * Copy the osflags (kernel arguments) into the consoles
-     * memory. (Presently Linux does not use the console service
-     * routine to get these command line arguments, but Tru64 and
-     * others do.)
-     */
-    if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
-        warn("writing addr starting from %#x", addr);
-        virtPort->writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
-                strlen(params()->boot_osflags.c_str()));
+void
+MipsSystem::initState()
+{
+    System::initState();
+    if (bootldr) {
+        if (!params()->gic_cpu_addr || !params()->flags_addr)
+            fatal("gic_cpu_addr && flags_addr must be set with bootloader\n");
+    } else {
+        // Set the initial PC to be at start of the kernel code
+        threadContexts[0]->pcState(kernelEntry);
     }
-
-    /**
-     * Set the hardware reset parameter block system type and revision
-     * information to Tsunami.
-     */
-    if (consoleSymtab->findAddress("m5_rpb", addr)) {
-        uint64_t data;
-        data = htog(params()->system_type);
-        virtPort->write(addr + 0x50, data);
-        data = htog(params()->system_rev);
-        virtPort->write(addr + 0x58, data);
-    } else {
-        panic("could not find hwrpb\n");
-    }
-#endif
 }
 
 MipsSystem::~MipsSystem()
 {
+    if (debugPrintkEvent)
+        delete debugPrintkEvent;
 }
 
-#if FULL_SYSTEM
-Addr
-MipsSystem::fixFuncEventAddr(Addr addr)
-{
-    return addr;
-}
-
-void
-MipsSystem::setMipsAccess(Addr access)
-{}
-
-#endif
-
-bool
-MipsSystem::breakpoint()
-{
-    return 0;
-}
-
-void
-MipsSystem::serialize(std::ostream &os)
-{
-    System::serialize(os);
-}
-
-
-void
-MipsSystem::unserialize(Checkpoint *cp, const std::string &section)
-{
-    System::unserialize(cp,section);
-}
 
 MipsSystem *
 MipsSystemParams::create()
diff -r f348cf78072c src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/tlb.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -330,7 +330,8 @@
       } else {
         VPN = ((vaddr >> 11) & 0xFFFFFFFC);
       }
-      uint8_t Asid = req->getAsid();
+      // req->getAsid cannot work --zxli
+      uint8_t Asid = tc->readMiscReg(MISCREG_ENTRYHI);
       if (misaligned) {
           // Unaligned address!
           return new AddressErrorFault(vaddr, false);
@@ -423,7 +424,8 @@
         if (smallPages == 1) {
             VPN = vaddr >> 11;
         }
-        uint8_t Asid = req->getAsid();
+        // req->getAsid cannot work --zxli
+        uint8_t Asid = tc->readMiscReg(MISCREG_ENTRYHI);
         PTE *pte = lookup(VPN, Asid);
         if (misaligned) {
             return new AddressErrorFault(vaddr, true);
diff -r f348cf78072c src/arch/mips/vtophys.cc
--- a/src/arch/mips/vtophys.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/vtophys.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -38,6 +38,7 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "mem/vport.hh"
+#include "debug/VtoPhys.hh"
 
 using namespace std;
 using namespace MipsISA;
diff -r f348cf78072c src/dev/mips/RealView.py
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/RealView.py	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,136 @@
+# Copyright (c) 2009 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+#          Gabe Black
+#          William Wang
+#          Zhengxing Li
+
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
+from Ide import *
+from Platform import Platform
+from Terminal import Terminal
+from Uart import Uart
+
+class AmbaDevice(BasicPioDevice):
+    type = 'AmbaDevice'
+    abstract = True
+    amba_id = Param.UInt32("ID of AMBA device for kernel detection")
+
+class AmbaIntDevice(AmbaDevice):
+    type = 'AmbaIntDevice'
+    abstract = True
+    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    int_num = Param.UInt32("Interrupt number that connects to GIC")
+    int_delay = Param.Latency("100ns",
+            "Time between action and interrupt generation by device")
+
+class AmbaDmaDevice(DmaDevice):
+    type = 'AmbaDmaDevice'
+    abstract = True
+    pio_addr = Param.Addr("Address for AMBA slave interface")
+    pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
+    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    int_num = Param.UInt32("Interrupt number that connects to GIC")
+    amba_id = Param.UInt32("ID of AMBA device for kernel detection")
+
+class RealViewCtrl(BasicPioDevice):
+    type = 'RealViewCtrl'
+    proc_id = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
+    idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
+
+class Gic(PioDevice):
+    type = 'Gic'
+    dist_addr = Param.Addr(0x1f001000, "Address for distributor")
+    cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
+    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
+    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
+    int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
+    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
+
+class AmbaFake(AmbaDevice):
+    type = 'AmbaFake'
+    ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
+    amba_id = 0;
+
+class Pl011(Uart):
+    type = 'Pl011'
+    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    int_num = Param.UInt32("Interrupt number that connects to GIC")
+    end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
+    int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
+
+class Sp804(AmbaDevice):
+    type = 'Sp804'
+    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    int_num0 = Param.UInt32("Interrupt number that connects to GIC")
+    clock0 = Param.Clock('1MHz', "Clock speed of the input")
+    int_num1 = Param.UInt32("Interrupt number that connects to GIC")
+    clock1 = Param.Clock('1MHz', "Clock speed of the input")
+    amba_id = 0x00141804
+
+class RealView(Platform):
+    type = 'RealView'
+    system = Param.System(Parent.any, "system")
+
+# Reference for memory map and interrupt number
+# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
+# Chapter 4: Programmer's Reference
+class RealViewPBX(RealView):
+    uart = Pl011(pio_addr=0x10009000, int_num=44)
+    realview_io = RealViewCtrl(pio_addr=0x10000000)
+    gic = Gic(dist_addr=0x1e001000, cpu_addr=0x1e000000)
+    timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
+    timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
+    sp810_fake    = AmbaFake(pio_addr=0x10001000, ignore_access=True)
+
+    # Attach I/O devices that are on chip
+    def attachOnChipIO(self, bus):
+       self.gic.pio = bus.port
+
+    # Attach I/O devices to specified bus object.  Can't do this
+    # earlier, since the bus object itself is typically defined at the
+    # System level.
+    def attachIO(self, bus):
+       self.uart.pio          = bus.port
+       self.realview_io.pio   = bus.port
+       self.timer0.pio        = bus.port
+       self.timer1.pio        = bus.port
+       self.sp810_fake.pio    = bus.port
diff -r f348cf78072c src/dev/mips/SConscript
--- a/src/dev/mips/SConscript	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/dev/mips/SConscript	Fri Jan 13 03:22:43 2012 +0800
@@ -28,15 +28,29 @@
 #
 # Authors: Steve Reinhardt
 #          Gabe Black
+#          Zhengxing Li
+#          Deyuan Guo
 
 Import('*')
 
 if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
-    SimObject('Malta.py')
+    SimObject('RealView.py')
 
-    DebugFlag('Malta')
+    Source('amba_device.cc')
+    Source('amba_fake.cc')
+    Source('gic.cc')
+    Source('pl011.cc')
+    Source('timer_sp804.cc')
+    Source('rv_ctrl.cc')
+    Source('realview.cc')
 
-    Source('malta.cc')
-    Source('malta_cchip.cc')
-    Source('malta_io.cc')
-    Source('malta_pchip.cc')
+    DebugFlag('AMBA')
+    DebugFlag('GIC')
+
+
+#    SimObject('Malta.py')
+#    DebugFlag('Malta')
+#    Source('malta.cc')
+#    Source('malta_cchip.cc')
+#    Source('malta_io.cc')
+#    Source('malta_pchip.cc')
diff -r f348cf78072c src/dev/mips/amba_device.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/amba_device.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+
+/** @file
+ * This is a base class for AMBA devices that have to respond to Device and
+ * Implementer ID calls.
+ */
+
+#ifndef __DEV_ARM_AMBA_DEVICE_HH__
+#define __DEV_ARM_AMBA_DEVICE_HH__
+
+#include "base/range.hh"
+#include "dev/mips/gic.hh"
+#include "dev/io_device.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "params/AmbaDevice.hh"
+#include "params/AmbaDmaDevice.hh"
+#include "params/AmbaIntDevice.hh"
+
+namespace AmbaDev {
+
+const int AMBA_PER_ID0 = 0xFE0;
+const int AMBA_PER_ID1 = 0xFE4;
+const int AMBA_PER_ID2 = 0xFE8;
+const int AMBA_PER_ID3 = 0xFEC;
+const int AMBA_CEL_ID0 = 0xFF0;
+const int AMBA_CEL_ID1 = 0xFF4;
+const int AMBA_CEL_ID2 = 0xFF8;
+const int AMBA_CEL_ID3 = 0xFFC;
+
+bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr);
+}
+
+class AmbaDevice : public BasicPioDevice
+{
+  protected:
+    uint64_t ambaId;
+
+  public:
+    typedef AmbaDeviceParams Params;
+    AmbaDevice(const Params *p);
+};
+
+class AmbaIntDevice : public AmbaDevice
+{
+  protected:
+    int intNum;
+    Gic *gic;
+    Tick intDelay;
+
+  public:
+    typedef AmbaIntDeviceParams Params;
+    AmbaIntDevice(const Params *p);
+};
+
+class AmbaDmaDevice : public DmaDevice
+{
+  protected:
+    uint64_t ambaId;
+    Addr     pioAddr;
+    Addr     pioSize;
+    Tick     pioDelay;
+    int      intNum;
+    Gic      *gic;
+
+  public:
+    typedef AmbaDmaDeviceParams Params;
+    AmbaDmaDevice(const Params *p);
+};
+
+
+#endif //__DEV_ARM_AMBA_DEVICE_HH__
diff -r f348cf78072c src/dev/mips/amba_device.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/amba_device.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "base/trace.hh"
+#include "debug/AMBA.hh"
+#include "dev/mips/amba_device.hh"
+#include "dev/mips/amba_fake.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+const uint64_t AmbaVendor = ULL(0xb105f00d00000000);
+
+AmbaDevice::AmbaDevice(const Params *p)
+    : BasicPioDevice(p), ambaId(AmbaVendor | p->amba_id)
+{
+}
+
+AmbaIntDevice::AmbaIntDevice(const Params *p)
+    : AmbaDevice(p), intNum(p->int_num), gic(p->gic), intDelay(p->int_delay)
+{
+}
+
+
+
+AmbaDmaDevice::AmbaDmaDevice(const Params *p)
+    : DmaDevice(p), ambaId(AmbaVendor | p->amba_id),
+      pioAddr(p->pio_addr), pioSize(0),
+      pioDelay(p->pio_latency),intNum(p->int_num), gic(p->gic)
+{
+}
+
+namespace AmbaDev {
+bool
+readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
+{
+    Addr daddr = pkt->getAddr() - pio_addr;
+    if (daddr < AMBA_PER_ID0 || daddr > AMBA_CEL_ID3)
+        return false;
+
+    pkt->allocate();
+
+    int byte = (daddr - AMBA_PER_ID0) << 1;
+    // Too noisy right now
+    DPRINTF(AMBA, "Returning %#x for offset %#x(%d)\n", (amba_id >> byte) & 0xFF,
+            pkt->getAddr() - pio_addr, byte);
+    assert(pkt->getSize() == 4);
+    pkt->set<uint32_t>((amba_id >> byte) & 0xFF);
+    return true;
+}
+
+} // namespace AmbaDev
diff -r f348cf78072c src/dev/mips/amba_fake.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/amba_fake.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+
+/** @file
+ * This device sits in memory and reponds appropriately so the linux kernel
+ * ignores the device it is trying to talk to. It is used so the kernel doesn't
+ * need to be modified and devices that we are not interested in will simply be
+ * skipped.
+ */
+
+#ifndef __DEV_ARM_AMBA_FAKE_H__
+#define __DEV_ARM_AMBA_FAKE_H__
+
+#include "base/range.hh"
+#include "dev/mips/amba_device.hh"
+#include "params/AmbaFake.hh"
+
+class AmbaFake : public AmbaDevice
+{
+  public:
+   typedef AmbaFakeParams Params;
+   const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+    AmbaFake(const Params *p);
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
+
+};
+
+#endif //__DEV_ARM_AMBA_FAKE_H__
diff -r f348cf78072c src/dev/mips/amba_fake.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/amba_fake.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "base/trace.hh"
+#include "debug/AMBA.hh"
+#include "dev/mips/amba_fake.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+using namespace AmbaDev;
+
+AmbaFake::AmbaFake(const Params *p)
+    : AmbaDevice(p)
+{
+    pioSize = 0xfff;
+}
+
+Tick
+AmbaFake::read(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+
+    Addr daddr = pkt->getAddr() - pioAddr;
+    pkt->allocate();
+
+    DPRINTF(AMBA, " read register %#x\n", daddr);
+
+    pkt->set<uint32_t>(0);
+    if (!readId(pkt, ambaId, pioAddr) && !params()->ignore_access)
+        panic("Tried to read AmbaFake at offset %#x that doesn't exist\n", daddr);
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+Tick
+AmbaFake::write(PacketPtr pkt)
+{
+
+    Addr daddr = pkt->getAddr() - pioAddr;
+    pkt->allocate();
+
+    if (!params()->ignore_access)
+        panic("Tried to write AmbaFake at offset %#x that doesn't exist\n", daddr);
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+
+AmbaFake *
+AmbaFakeParams::create()
+{
+    return new AmbaFake(this);
+}
diff -r f348cf78072c src/dev/mips/gic.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/gic.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+
+/** @file
+ * Implementiation of a PL390 GIC
+ */
+
+#ifndef __DEV_ARM_GIC_H__
+#define __DEV_ARM_GIC_H__
+
+#include "base/bitunion.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
+#include "dev/platform.hh"
+#include "cpu/intr_control.hh"
+#include "params/Gic.hh"
+
+/** @todo this code only assumes one processor for now. Low word
+ * of intEnabled and pendingInt need to be replicated per CPU.
+ * bottom 31 interrupts (7 words) need to be replicated for
+ * for interrupt priority register, processor target registers
+ * interrupt config registers  */
+
+class Gic : public PioDevice
+{
+  protected:
+    // distributor memory addresses
+    static const int ICDDCR     = 0x000; // control register
+    static const int ICDICTR    = 0x004; // controller type
+    static const int ICDIIDR    = 0x008; // implementer id
+    static const int ICDISER_ST = 0x100; // interrupt set enable
+    static const int ICDISER_ED = 0x17c;
+    static const int ICDICER_ST = 0x180; // interrupt clear enable
+    static const int ICDICER_ED = 0x1fc;
+    static const int ICDISPR_ST = 0x200; // set pending interrupt
+    static const int ICDISPR_ED = 0x27c;
+    static const int ICDICPR_ST = 0x280; // clear pending interrupt
+    static const int ICDICPR_ED = 0x2fc;
+    static const int ICDABR_ST  = 0x300; // active bit registers
+    static const int ICDABR_ED  = 0x37c;
+    static const int ICDIPR_ST  = 0x400; // interrupt priority registers
+    static const int ICDIPR_ED  = 0x7f8;
+    static const int ICDIPTR_ST = 0x800; // processor target registers
+    static const int ICDIPTR_ED = 0xbf8;
+    static const int ICDICFR_ST = 0xc00; // interrupt config registers
+    static const int ICDICFR_ED = 0xcfc;
+    static const int ICDSGIR    = 0xf00; // software generated interrupt
+    static const int DIST_SIZE  = 0xfff;
+
+    // cpu memory addressesa
+    static const int ICCICR  = 0x00; // CPU control register
+    static const int ICCPMR  = 0x04; // Interrupt priority mask
+    static const int ICCBPR  = 0x08; // binary point register
+    static const int ICCIAR  = 0x0C; // interrupt ack register
+    static const int ICCEOIR = 0x10; // end of interrupt
+    static const int ICCRPR  = 0x14; // runing priority
+    static const int ICCHPIR = 0x18; // highest pending interrupt
+    static const int ICCABPR = 0x1c; // aliased binary point
+    static const int ICCIIDR = 0xfc; // cpu interface id register
+    static const int CPU_SIZE  = 0xff;
+
+    static const int SGI_MAX = 16;  // Number of Software Gen Interrupts
+
+    /** Mask off SGI's when setting/clearing pending bits */
+    static const int SGI_MASK = 0xFFFF0000;
+
+    /** Mask for bits that config N:N mode in ICDICFR's */
+    static const int NN_CONFIG_MASK = 0x55555555;
+
+    static const int CPU_MAX = 8;   // Max number of supported CPU interfaces
+    static const int SPURIOUS_INT = 1023;
+    static const int INT_BITS_MAX = 32;
+    static const int INT_LINES_MAX = 1020;
+
+    BitUnion32(SWI)
+        Bitfield<3,0> sgi_id;
+        Bitfield<23,16> cpu_list;
+        Bitfield<25,24> list_type;
+    EndBitUnion(SWI)
+
+    BitUnion32(IAR)
+        Bitfield<9,0> ack_id;
+        Bitfield<12,10> cpu_id;
+    EndBitUnion(IAR)
+
+    /** Distributor address GIC listens at */
+    Addr distAddr;
+
+    /** CPU address GIC listens at */
+    /** @todo is this one per cpu? */
+    Addr cpuAddr;
+
+    /** Latency for a distributor operation */
+    Tick distPioDelay;
+
+    /** Latency for a cpu operation */
+    Tick cpuPioDelay;
+
+    /** Latency for a interrupt to get to CPU */
+    Tick intLatency;
+
+    /** Gic enabled */
+    bool enabled;
+
+    /** Number of itLines enabled */
+    uint32_t itLines;
+
+    uint32_t itLinesLog2;
+
+    /** interrupt enable bits for all possible 1020 interupts.
+     * one bit per interrupt, 32 bit per word = 32 words */
+    uint32_t intEnabled[INT_BITS_MAX];
+
+    /** interrupt pending bits for all possible 1020 interupts.
+     * one bit per interrupt, 32 bit per word = 32 words */
+    uint32_t pendingInt[INT_BITS_MAX];
+
+    /** interrupt active bits for all possible 1020 interupts.
+     * one bit per interrupt, 32 bit per word = 32 words */
+    uint32_t activeInt[INT_BITS_MAX];
+
+    /** read only running priroity register, 1 per cpu*/
+    uint32_t iccrpr[CPU_MAX];
+
+    /** an 8 bit priority (lower is higher priority) for each
+     * of the 1020 possible supported interrupts.
+     */
+    uint8_t intPriority[INT_LINES_MAX];
+
+    /** an 8 bit cpu target id for each shared peripheral interrupt
+     * of the 1020 possible supported interrupts.
+     */
+    uint8_t cpuTarget[INT_LINES_MAX];
+
+    /** 2 bit per interrupt signaling if it's level or edge sensitive
+     * and if it is 1:N or N:N */
+    uint32_t intConfig[INT_BITS_MAX*2];
+
+    /** CPU enabled */
+    bool cpuEnabled[CPU_MAX];
+
+    /** CPU priority */
+    uint8_t cpuPriority[CPU_MAX];
+
+    /** Binary point registers */
+    uint8_t cpuBpr[CPU_MAX];
+
+    /** highest interrupt that is interrupting CPU */
+    uint32_t cpuHighestInt[CPU_MAX];
+
+    /** One bit per cpu per software interrupt that is pending for each possible
+     * sgi source. Indexed by SGI number. Each byte in generating cpu id and
+     * bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
+     * for CPU 2. */
+    uint64_t cpuSgiPending[SGI_MAX];
+    uint64_t cpuSgiActive[SGI_MAX];
+
+    /** IRQ Enable Used for debug */
+    bool irqEnable;
+
+    /** software generated interrupt
+     * @param data data to decode that indicates which cpus to interrupt
+     */
+    void softInt(int ctx_id, SWI swi);
+
+    /** See if some processor interrupt flags need to be enabled/disabled
+     * @param hint which set of interrupts needs to be checked
+     */
+    void updateIntState(int hint);
+
+    /** Update the register that records priority of the highest priority
+     *  active interrupt*/
+    void updateRunPri();
+
+    /** generate a bit mask to check cpuSgi for an interrupt. */
+    uint64_t genSwiMask(int cpu);
+
+    int intNumToWord(int num) const { return num >> 5; }
+    int intNumToBit(int num) const { return num % 32; }
+
+    /** Event definition to post interrupt to CPU after a delay
+    */
+    class PostIntEvent : public Event
+    {
+      private:
+        uint32_t cpu;
+        Platform *platform;
+      public:
+        PostIntEvent( uint32_t c, Platform* p)
+            : cpu(c), platform(p)
+        { }
+        void process() { platform->intrctrl->post(cpu, MipsISA::IT_HARD_INT0, 0);}
+        const char *description() const { return "Post Interrupt to CPU"; }
+    };
+    PostIntEvent *postIntEvent[CPU_MAX];
+
+  public:
+   typedef GicParams Params;
+   const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+    Gic(const Params *p);
+
+    /** Return the address ranges used by the Gic
+     * This is the distributor address + all cpu addresses
+     */
+    virtual void addressRanges(AddrRangeList &range_list);
+
+    /** A PIO read to the device, immediately split up into
+     * readDistributor() or readCpu()
+     */
+    virtual Tick read(PacketPtr pkt);
+
+    /** A PIO read to the device, immediately split up into
+     * writeDistributor() or writeCpu()
+     */
+    virtual Tick write(PacketPtr pkt);
+
+    /** Handle a read to the distributor poriton of the GIC
+     * @param pkt packet to respond to
+     */
+    Tick readDistributor(PacketPtr pkt);
+
+    /** Handle a read to the cpu poriton of the GIC
+     * @param pkt packet to respond to
+     */
+    Tick readCpu(PacketPtr pkt);
+
+    /** Handle a write to the distributor poriton of the GIC
+     * @param pkt packet to respond to
+     */
+    Tick writeDistributor(PacketPtr pkt);
+
+    /** Handle a write to the cpu poriton of the GIC
+     * @param pkt packet to respond to
+     */
+    Tick writeCpu(PacketPtr pkt);
+
+    /** Post an interrupt from a device that is connected to the Gic.
+     * Depending on the configuration, the gic will pass this interrupt
+     * on through to a CPU.
+     * @param number number of interrupt to send */
+    void sendInt(uint32_t number);
+
+    /** Clear an interrupt from a device that is connected to the Gic
+     * Depending on the configuration, the gic may de-assert it's cpu line
+     * @param number number of interrupt to send */
+    void clearInt(uint32_t number);
+
+    /** Post an interrupt to a CPU
+     */
+    void postInt(uint32_t cpu, Tick when);
+
+    /* Various functions fer testing and debugging */
+    void driveSPI(uint32_t spi);
+    void driveLegIRQ(bool state);
+    void driveLegFIQ(bool state);
+    void driveIrqEn(bool state);
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+};
+
+#endif //__DEV_ARM_GIC_H__
diff -r f348cf78072c src/dev/mips/gic.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/gic.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Prakash Ramrakhyani
+ */
+
+#include "base/trace.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/GIC.hh"
+#include "debug/IPI.hh"
+#include "dev/mips/gic.hh"
+#include "dev/terminal.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "debug/Interrupt.hh"
+
+Gic::Gic(const Params *p)
+    : PioDevice(p),distAddr(p->dist_addr), cpuAddr(p->cpu_addr),
+      distPioDelay(p->dist_pio_delay), cpuPioDelay(p->cpu_pio_delay),
+      intLatency(p->int_latency), enabled(false), itLines(p->it_lines)
+{
+    itLinesLog2 = ceilLog2(itLines);
+
+    for (int x = 0; x < CPU_MAX; x++) {
+        cpuEnabled[x] = false;
+        cpuPriority[x] = 0xff;
+        cpuBpr[x] = 0;
+        // Initialize cpu highest int
+        cpuHighestInt[x] = SPURIOUS_INT;
+        postIntEvent[x] = new PostIntEvent(x, p->platform);
+    }
+    DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n", cpuEnabled[0],
+            cpuEnabled[1]);
+
+    for (int x = 0; x < INT_BITS_MAX; x++) {
+        intEnabled[x] = 0;
+        pendingInt[x] = 0;
+        activeInt[x] = 0;
+    }
+
+    for (int x = 0; x < INT_LINES_MAX; x++) {
+        intPriority[x] = 0;
+        cpuTarget[x] = 0;
+    }
+
+    for (int x = 0; x < INT_BITS_MAX*2; x++) {
+        intConfig[x] = 0;
+    }
+
+    for (int x = 0; x < SGI_MAX; x++) {
+        cpuSgiActive[x] = 0;
+        cpuSgiPending[x] = 0;
+    }
+}
+
+Tick
+Gic::read(PacketPtr pkt)
+{
+
+    Addr addr = pkt->getAddr();
+
+    if (addr >= distAddr && addr < distAddr + DIST_SIZE)
+        return readDistributor(pkt);
+    else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
+        return readCpu(pkt);
+    else
+        panic("Read to unknown address %#x\n", pkt->getAddr());
+}
+
+
+Tick
+Gic::write(PacketPtr pkt)
+{
+
+    Addr addr = pkt->getAddr();
+
+    if (addr >= distAddr && addr < distAddr + DIST_SIZE)
+        return writeDistributor(pkt);
+    else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
+        return writeCpu(pkt);
+    else
+        panic("Write to unknown address %#x\n", pkt->getAddr());
+}
+
+Tick
+Gic::readDistributor(PacketPtr pkt)
+{
+    Addr daddr = pkt->getAddr() - distAddr;
+    pkt->allocate();
+
+    DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
+
+    if (daddr >= ICDISER_ST && daddr < ICDISER_ED + 4) {
+        assert((daddr-ICDISER_ST) >> 2 < 32);
+        pkt->set<uint32_t>(intEnabled[(daddr-ICDISER_ST)>>2]);
+        goto done;
+    }
+
+    if (daddr >= ICDICER_ST && daddr < ICDICER_ED + 4) {
+        assert((daddr-ICDICER_ST) >> 2 < 32);
+        pkt->set<uint32_t>(intEnabled[(daddr-ICDICER_ST)>>2]);
+        goto done;
+    }
+
+    if (daddr >= ICDISPR_ST && daddr < ICDISPR_ED + 4) {
+        assert((daddr-ICDISPR_ST) >> 2 < 32);
+        pkt->set<uint32_t>(pendingInt[(daddr-ICDISPR_ST)>>2]);
+        goto done;
+    }
+
+    if (daddr >= ICDICPR_ST && daddr < ICDICPR_ED + 4) {
+        assert((daddr-ICDICPR_ST) >> 2 < 32);
+        pkt->set<uint32_t>(pendingInt[(daddr-ICDICPR_ST)>>2]);
+        goto done;
+    }
+
+    if (daddr >= ICDABR_ST && daddr < ICDABR_ED + 4) {
+        assert((daddr-ICDABR_ST) >> 2 < 32);
+        pkt->set<uint32_t>(activeInt[(daddr-ICDABR_ST)>>2]);
+        goto done;
+    }
+
+    if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
+        Addr int_num;
+        int_num = daddr - ICDIPR_ST;
+        assert(int_num < INT_LINES_MAX);
+        DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",int_num);
+        switch(pkt->getSize()) {
+          case 1:
+            pkt->set<uint8_t>(intPriority[int_num]);
+            break;
+          case 2:
+            pkt->set<uint16_t>(intPriority[int_num] |
+                               intPriority[int_num+1] << 8);
+            break;
+          case 4:
+            pkt->set<uint32_t>(intPriority[int_num] |
+                               intPriority[int_num+1] << 8 |
+                               intPriority[int_num+2] << 16 |
+                               intPriority[int_num+3] << 24);
+            break;
+          default:
+            panic("Invalid size while reading priority regs in GIC: %d\n",
+                   pkt->getSize());
+        }
+        goto done;
+    }
+
+    if (daddr >= ICDIPTR_ST && daddr < ICDIPTR_ED + 4) {
+        Addr int_num;
+        int_num = (daddr-ICDIPTR_ST) ;
+        DPRINTF(GIC, "Reading processor target register for int# %#x \n",
+                 int_num);
+        assert(int_num < INT_LINES_MAX);
+
+        // First 31 interrupts only target single processor (SGI)
+        if (int_num > 31) {
+            if (pkt->getSize() == 1) {
+                pkt->set<uint8_t>(cpuTarget[int_num]);
+            } else {
+                assert(pkt->getSize() == 4);
+                int_num = mbits(int_num, 31, 2);
+                pkt->set<uint32_t>(cpuTarget[int_num] |
+                                   cpuTarget[int_num+1] << 8 |
+                                   cpuTarget[int_num+2] << 16 |
+                                   cpuTarget[int_num+3] << 24) ;
+            }
+        } else {
+            int ctx_id = pkt->req->contextId();
+            assert(ctx_id < sys->numRunningContexts());
+            pkt->set<uint32_t>(ctx_id);
+        }
+        goto done;
+    }
+
+    if (daddr >= ICDICFR_ST && daddr < ICDICFR_ED + 4) {
+        assert((daddr-ICDICFR_ST) >> 2 < 64);
+        /** @todo software generated interrutps and PPIs
+         * can't be configured in some ways
+         */
+        pkt->set<uint32_t>(intConfig[(daddr-ICDICFR_ST)>>2]);
+        goto done;
+    }
+
+    switch(daddr) {
+      case ICDDCR:
+        pkt->set<uint32_t>(enabled);
+        break;
+      case ICDICTR:
+        uint32_t tmp;
+        tmp = ((sys->numRunningContexts() - 1) << 5) |
+              (itLines/INT_BITS_MAX -1);
+        pkt->set<uint32_t>(tmp);
+        break;
+      default:
+        panic("Tried to read Gic distributor at offset %#x\n", daddr);
+        break;
+    }
+done:
+    pkt->makeAtomicResponse();
+    return distPioDelay;
+}
+
+Tick
+Gic::readCpu(PacketPtr pkt)
+{
+    Addr daddr = pkt->getAddr() - cpuAddr;
+    pkt->allocate();
+
+    assert(pkt->req->hasContextId());
+    int ctx_id = pkt->req->contextId();
+    assert(ctx_id < sys->numRunningContexts());
+
+    DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
+            ctx_id);
+
+    switch(daddr) {
+      case ICCICR:
+        pkt->set<uint32_t>(cpuEnabled[ctx_id]);
+        break;
+      case ICCPMR:
+        pkt->set<uint32_t>(cpuPriority[ctx_id]);
+        break;
+      case ICCBPR:
+        pkt->set<uint32_t>(cpuBpr[ctx_id]);
+        break;
+      case ICCIAR:
+        if (enabled && cpuEnabled[ctx_id]) {
+            int active_int = cpuHighestInt[ctx_id];
+            IAR iar = 0;
+            iar.ack_id = active_int;
+            iar.cpu_id = 0;
+            if (active_int < SGI_MAX) {
+                // this is a software interrupt from another CPU
+                if (!cpuSgiPending[active_int])
+                    panic("Interrupt %d active but no CPU generated it?\n",
+                            active_int);
+                for (int x = 0; x < CPU_MAX; x++) {
+                    // See which CPU generated the interrupt
+                    uint8_t cpugen =
+                        bits(cpuSgiPending[active_int], 7 + 8 * x, 8 * x);
+                    if (cpugen & (1 << ctx_id)) {
+                        iar.cpu_id = x;
+                        break;
+                    }
+                }
+                uint64_t sgi_num = ULL(1) << (ctx_id + 8 * iar.cpu_id);
+                cpuSgiActive[iar.ack_id] |= sgi_num;
+                cpuSgiPending[iar.ack_id] &= ~sgi_num;
+            } else {
+                uint32_t int_num = 1 << intNumToBit(cpuHighestInt[ctx_id]);
+                activeInt[intNumToWord(cpuHighestInt[ctx_id])] |= int_num;
+                updateRunPri();
+                pendingInt[intNumToWord(cpuHighestInt[ctx_id])] &= ~int_num;
+            }
+
+            DPRINTF(Interrupt,"CPU %d reading IAR.id=%d IAR.cpu=%d, iar=0x%x\n",
+                    ctx_id, iar.ack_id, iar.cpu_id, iar);
+            cpuHighestInt[ctx_id] = SPURIOUS_INT;
+            updateIntState(-1);
+            pkt->set<uint32_t>(iar);
+            platform->intrctrl->clear(ctx_id, MipsISA::IT_HARD_INT0, 0);
+        } else {
+             pkt->set<uint32_t>(SPURIOUS_INT);
+        }
+
+        break;
+      case ICCRPR:
+        pkt->set<uint32_t>(iccrpr[0]);
+        break;
+      case ICCHPIR:
+        pkt->set<uint32_t>(0);
+        panic("Need to implement HPIR");
+        break;
+      default:
+        panic("Tried to read Gic cpu at offset %#x\n", daddr);
+        break;
+    }
+    pkt->makeAtomicResponse();
+    return cpuPioDelay;
+}
+
+
+Tick
+Gic::writeDistributor(PacketPtr pkt)
+{
+    Addr daddr = pkt->getAddr() - distAddr;
+    pkt->allocate();
+
+    assert(pkt->req->hasContextId());
+    int ctx_id = pkt->req->contextId();
+
+    DPRINTF(GIC, "gic distributor write register %#x size %#x value %#x \n",
+            daddr, pkt->getSize(), pkt->get<uint32_t>());
+
+    if (daddr >= ICDISER_ST && daddr < ICDISER_ED + 4) {
+        assert((daddr-ICDISER_ST) >> 2 < 32);
+        intEnabled[(daddr-ICDISER_ST) >> 2] |= pkt->get<uint32_t>();
+        goto done;
+    }
+
+    if (daddr >= ICDICER_ST && daddr < ICDICER_ED + 4) {
+        assert((daddr-ICDICER_ST) >> 2 < 32);
+        intEnabled[(daddr-ICDICER_ST) >> 2] &= ~pkt->get<uint32_t>();
+        goto done;
+    }
+
+    if (daddr >= ICDISPR_ST && daddr < ICDISPR_ED + 4) {
+        assert((daddr-ICDISPR_ST) >> 2 < 32);
+        pendingInt[(daddr-ICDISPR_ST) >> 2] |= pkt->get<uint32_t>();
+        pendingInt[0] &= SGI_MASK; // Don't allow SGIs to be changed
+        updateIntState((daddr-ICDISPR_ST) >> 2);
+        goto done;
+    }
+
+    if (daddr >= ICDICPR_ST && daddr < ICDICPR_ED + 4) {
+        assert((daddr-ICDICPR_ST) >> 2 < 32);
+        pendingInt[(daddr-ICDICPR_ST) >> 2] &= ~pkt->get<uint32_t>();
+        pendingInt[0] &= SGI_MASK; // Don't allow SGIs to be changed
+        updateIntState((daddr-ICDICPR_ST) >> 2);
+        goto done;
+    }
+
+    if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
+        Addr int_num = daddr - ICDIPR_ST;
+        assert(int_num < INT_LINES_MAX);
+        uint32_t tmp;
+        switch(pkt->getSize()) {
+          case 1:
+            tmp = pkt->get<uint8_t>();
+            intPriority[int_num] = bits(tmp, 7, 0);
+            break;
+          case 2:
+            tmp = pkt->get<uint16_t>();
+            intPriority[int_num] = bits(tmp, 7, 0);
+            intPriority[int_num + 1] = bits(tmp, 15, 8);
+            break;
+          case 4:
+            tmp = pkt->get<uint32_t>();
+            intPriority[int_num] = bits(tmp, 7, 0);
+            intPriority[int_num + 1] = bits(tmp, 15, 8);
+            intPriority[int_num + 2] = bits(tmp, 23, 16);
+            intPriority[int_num + 3] = bits(tmp, 31, 24);
+            break;
+          default:
+            panic("Invalid size when writing to priority regs in Gic: %d\n",
+                   pkt->getSize());
+        }
+
+        updateIntState(-1);
+        updateRunPri();
+        goto done;
+    }
+
+    if (daddr >= ICDIPTR_ST && daddr < ICDIPTR_ED + 4) {
+        Addr int_num = (daddr-ICDIPTR_ST) ;
+        assert(int_num < INT_LINES_MAX);
+        // First 31 interrupts only target single processor
+        if (int_num >= SGI_MAX) {
+            if (pkt->getSize() == 1) {
+                uint8_t tmp = pkt->get<uint8_t>();
+                cpuTarget[int_num] = tmp & 0xff;
+            } else {
+                assert (pkt->getSize() == 4);
+                int_num = mbits(int_num, 31, 2);
+                uint32_t tmp = pkt->get<uint32_t>();
+                cpuTarget[int_num]   = bits(tmp, 7, 0);
+                cpuTarget[int_num+1] = bits(tmp, 15, 8);
+                cpuTarget[int_num+2] = bits(tmp, 23, 16);
+                cpuTarget[int_num+3] = bits(tmp, 31, 24);
+            }
+            updateIntState((daddr-ICDIPTR_ST)>>2);
+        }
+        goto done;
+    }
+
+    if (daddr >= ICDICFR_ST && daddr < ICDICFR_ED + 4) {
+        assert((daddr-ICDICFR_ST) >> 2 < 64);
+        intConfig[(daddr-ICDICFR_ST)>>2] = pkt->get<uint32_t>();
+        if (pkt->get<uint32_t>() & NN_CONFIG_MASK)
+            warn("GIC N:N mode selected and not supported at this time\n");
+        goto done;
+    }
+
+    switch(daddr) {
+      case ICDDCR:
+        enabled = pkt->get<uint32_t>();
+        DPRINTF(Interrupt, "Distributor enable flag set to = %d\n", enabled);
+        break;
+      case ICDSGIR:
+        softInt(ctx_id, pkt->get<uint32_t>());
+        break;
+      default:
+        panic("Tried to write Gic distributor at offset %#x\n", daddr);
+        break;
+    }
+
+done:
+    pkt->makeAtomicResponse();
+    return distPioDelay;
+}
+
+Tick
+Gic::writeCpu(PacketPtr pkt)
+{
+    Addr daddr = pkt->getAddr() - cpuAddr;
+    pkt->allocate();
+
+    assert(pkt->req->hasContextId());
+    int ctx_id = pkt->req->contextId();
+    IAR iar;
+
+    DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n",
+            ctx_id, daddr, pkt->get<uint32_t>());
+
+    switch(daddr) {
+      case ICCICR:
+        cpuEnabled[ctx_id] = pkt->get<uint32_t>();
+        break;
+      case ICCPMR:
+        cpuPriority[ctx_id] = pkt->get<uint32_t>();
+        break;
+      case ICCBPR:
+        cpuBpr[ctx_id] = pkt->get<uint32_t>();
+        break;
+      case ICCEOIR:
+        iar = pkt->get<uint32_t>();
+        if (iar.ack_id < SGI_MAX) {
+            // Clear out the bit that corrseponds to the cleared int
+            uint64_t clr_int = ULL(1) << (ctx_id + 8 * iar.cpu_id);
+            if (!(cpuSgiActive[iar.ack_id] & clr_int))
+                panic("Done handling a SGI that isn't active?\n");
+            cpuSgiActive[iar.ack_id] &= ~clr_int;
+        } else {
+            uint32_t int_num = 1 << intNumToBit(iar.ack_id);
+            if (!(activeInt[intNumToWord(iar.ack_id)] & int_num))
+                panic("Done handling interrupt that isn't active?\n");
+            activeInt[intNumToWord(iar.ack_id)] &= ~int_num;
+        }
+        updateRunPri();
+        DPRINTF(Interrupt, "CPU %d done handling intr IAR = %d from cpu %d\n",
+                ctx_id, iar.ack_id, iar.cpu_id);
+        break;
+      default:
+        panic("Tried to write Gic cpu at offset %#x\n", daddr);
+        break;
+    }
+    if (cpuEnabled[ctx_id]) updateIntState(-1);
+    pkt->makeAtomicResponse();
+    return cpuPioDelay;
+}
+
+void
+Gic::softInt(int ctx_id, SWI swi)
+{
+    switch (swi.list_type) {
+      case 1:
+        // interrupt all
+        uint8_t cpu_list;
+        cpu_list = 0;
+        for (int x = 0; x < CPU_MAX; x++)
+            cpu_list |= cpuEnabled[x] ? 1 << x : 0;
+        swi.cpu_list = cpu_list;
+        break;
+      case 2:
+        // interrupt requesting cpu only
+        swi.cpu_list = 1 << ctx_id;
+        break;
+        // else interrupt cpus specified
+    }
+
+    DPRINTF(IPI, "Generating softIRQ from CPU %d for %#x\n", ctx_id,
+            swi.cpu_list);
+    for (int i = 0; i < CPU_MAX; i++) {
+        DPRINTF(IPI, "Processing CPU %d\n", i);
+        if (!cpuEnabled[i])
+            continue;
+        if (swi.cpu_list & (1 << i))
+            cpuSgiPending[swi.sgi_id] |= (1 << i) << (8 * ctx_id);
+        DPRINTF(IPI, "SGI[%d]=%#x\n", swi.sgi_id, cpuSgiPending[swi.sgi_id]);
+    }
+    updateIntState(-1);
+}
+
+uint64_t
+Gic::genSwiMask(int cpu)
+{
+    if (cpu > 7)
+        panic("Invalid CPU ID\n");
+    return ULL(0x0101010101010101) << cpu;
+}
+
+void
+Gic::updateIntState(int hint)
+{
+    for (int cpu = 0; cpu < CPU_MAX; cpu++) {
+        if (!cpuEnabled[cpu])
+            continue;
+        if (cpu >= sys->numContexts())
+            break;
+
+        /*@todo use hint to do less work. */
+        int highest_int = SPURIOUS_INT;
+        // Priorities below that set in ICCPMR can be ignored
+        uint8_t highest_pri = cpuPriority[cpu];
+
+        // Check SGIs
+        for (int swi = 0; swi < SGI_MAX; swi++) {
+            if (!cpuSgiPending[swi])
+                continue;
+            if (cpuSgiPending[swi] & genSwiMask(cpu))
+                if (highest_pri > intPriority[swi]) {
+                    highest_pri = intPriority[swi];
+                    highest_int = swi;
+                }
+        }
+
+        bool mp_sys = sys->numRunningContexts() > 1;
+        // Check other ints
+        for (int x = 0; x < (itLines/INT_BITS_MAX) ; x++) {
+            if (intEnabled[x] & pendingInt[x]) {
+                for (int y = 0; y < INT_BITS_MAX; y++) {
+                   uint32_t int_nm = x * INT_BITS_MAX + y;
+                   DPRINTF(GIC, "Checking for interrupt# %d \n",int_nm);
+                    /* Set current pending int as highest int for current cpu
+                       if the interrupt's priority higher than current prioirty
+                       and if currrent cpu is the target (for mp configs only)
+                     */
+                    if ((bits(intEnabled[x], y) & bits(pendingInt[x], y)) &&
+                        (intPriority[int_nm] < highest_pri))
+                        if (mp_sys || (cpuTarget[int_nm] & (1 << cpu))) {
+                            highest_pri = intPriority[int_nm];
+                            highest_int = int_nm;
+                        }
+                }
+            }
+        }
+
+        cpuHighestInt[cpu] = highest_int;
+
+        if (highest_int == SPURIOUS_INT)
+            continue;
+
+        /* @todo make this work for more than one cpu, need to handle 1:N, N:N
+         * models */
+        if (enabled && cpuEnabled[cpu] && (highest_pri < cpuPriority[cpu]) &&
+            !(activeInt[intNumToWord(highest_int)]
+            & (1 << intNumToBit(highest_int)))) {
+
+            DPRINTF(Interrupt, "Posting interrupt %d to cpu%d\n", highest_int,
+                    cpu);
+            postInt(cpu, curTick() + intLatency);
+        }
+    }
+}
+
+void
+Gic::updateRunPri()
+{
+    for (int cpu = 0; cpu < CPU_MAX; cpu++) {
+        uint8_t maxPriority = 0xff;
+        for (int i = 0 ; i < itLines ; i++){
+            if (i < SGI_MAX) {
+                if ((cpuSgiActive[i] & genSwiMask(cpu)) &&
+                        (intPriority[i] < maxPriority))
+                    maxPriority = intPriority[i];
+            } else {
+                if (activeInt[intNumToWord(i)] & (1 << intNumToBit(i)))
+                    if (intPriority[i] < maxPriority)
+                        maxPriority = intPriority[i];
+            }
+        }
+        iccrpr[cpu] = maxPriority;
+    }
+}
+
+void
+Gic::sendInt(uint32_t num)
+{
+    DPRINTF(Interrupt, "Received Interupt number %d,  cpuTarget %#x: \n",
+            num, cpuTarget[num]);
+    if (cpuTarget[num] & (cpuTarget[num] - 1))
+        panic("Multiple targets for peripheral interrupts is not supported\n");
+    pendingInt[intNumToWord(num)] |= 1 << intNumToBit(num);
+    updateIntState(intNumToWord(num));
+
+}
+
+void
+Gic::clearInt(uint32_t number)
+{
+    /* @todo assume edge triggered only at the moment. Nothing to do. */
+}
+
+void
+Gic::postInt(uint32_t cpu, Tick when)
+{
+    if (!(postIntEvent[cpu]->scheduled()))
+        eventq->schedule(postIntEvent[cpu], when);
+}
+
+void
+Gic::addressRanges(AddrRangeList &range_list)
+{
+    range_list.clear();
+    range_list.push_back(RangeSize(distAddr, DIST_SIZE));
+    range_list.push_back(RangeSize(cpuAddr, CPU_SIZE));
+}
+
+
+void
+Gic::serialize(std::ostream &os)
+{
+    DPRINTF(Checkpoint, "Serializing Arm GIC\n");
+
+    SERIALIZE_SCALAR(distAddr);
+    SERIALIZE_SCALAR(cpuAddr);
+    SERIALIZE_SCALAR(distPioDelay);
+    SERIALIZE_SCALAR(cpuPioDelay);
+    SERIALIZE_SCALAR(enabled);
+    SERIALIZE_SCALAR(itLines);
+    SERIALIZE_SCALAR(itLinesLog2);
+    SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX);
+    SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX);
+    SERIALIZE_ARRAY(activeInt, INT_BITS_MAX);
+    SERIALIZE_ARRAY(iccrpr, CPU_MAX);
+    SERIALIZE_ARRAY(intPriority, INT_LINES_MAX);
+    SERIALIZE_ARRAY(cpuTarget, INT_LINES_MAX);
+    SERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
+    SERIALIZE_ARRAY(cpuEnabled, CPU_MAX);
+    SERIALIZE_ARRAY(cpuPriority, CPU_MAX);
+    SERIALIZE_ARRAY(cpuBpr, CPU_MAX);
+    SERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);
+    SERIALIZE_ARRAY(cpuSgiActive, SGI_MAX);
+    SERIALIZE_ARRAY(cpuSgiPending, SGI_MAX);
+    SERIALIZE_SCALAR(irqEnable);
+    Tick interrupt_time[CPU_MAX];
+    for (uint32_t cpu = 0; cpu < CPU_MAX; cpu++) {
+        interrupt_time[cpu] = 0;
+        if (postIntEvent[cpu]->scheduled()) {
+            interrupt_time[cpu] = postIntEvent[cpu]->when();
+        }
+    }
+    SERIALIZE_ARRAY(interrupt_time, CPU_MAX);
+
+}
+
+void
+Gic::unserialize(Checkpoint *cp, const std::string &section)
+{
+    DPRINTF(Checkpoint, "Unserializing Arm GIC\n");
+
+    UNSERIALIZE_SCALAR(distAddr);
+    UNSERIALIZE_SCALAR(cpuAddr);
+    UNSERIALIZE_SCALAR(distPioDelay);
+    UNSERIALIZE_SCALAR(cpuPioDelay);
+    UNSERIALIZE_SCALAR(enabled);
+    UNSERIALIZE_SCALAR(itLines);
+    UNSERIALIZE_SCALAR(itLinesLog2);
+    UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX);
+    UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX);
+    UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX);
+    UNSERIALIZE_ARRAY(iccrpr, CPU_MAX);
+    UNSERIALIZE_ARRAY(intPriority, INT_LINES_MAX);
+    UNSERIALIZE_ARRAY(cpuTarget, INT_LINES_MAX);
+    UNSERIALIZE_ARRAY(intConfig, INT_BITS_MAX * 2);
+    UNSERIALIZE_ARRAY(cpuEnabled, CPU_MAX);
+    UNSERIALIZE_ARRAY(cpuPriority, CPU_MAX);
+    UNSERIALIZE_ARRAY(cpuBpr, CPU_MAX);
+    UNSERIALIZE_ARRAY(cpuHighestInt, CPU_MAX);
+    UNSERIALIZE_ARRAY(cpuSgiActive, SGI_MAX);
+    UNSERIALIZE_ARRAY(cpuSgiPending, SGI_MAX);
+    UNSERIALIZE_SCALAR(irqEnable);
+
+    Tick interrupt_time[CPU_MAX];
+    UNSERIALIZE_ARRAY(interrupt_time, CPU_MAX);
+
+    for (uint32_t cpu = 0; cpu < CPU_MAX; cpu++) {
+        if (interrupt_time[cpu])
+            schedule(postIntEvent[cpu], interrupt_time[cpu]);
+    }
+
+}
+
+Gic *
+GicParams::create()
+{
+    return new Gic(this);
+}
+
+/* Functions for debugging and testing */
+void
+Gic::driveSPI(unsigned int spiVect)
+{
+    DPRINTF(GIC, "Received SPI Vector:%x Enable: %d\n", spiVect, irqEnable);
+    pendingInt[1] |= spiVect;
+    if (irqEnable && enabled) {
+        updateIntState(-1);
+    }
+}
+
+void
+Gic::driveIrqEn( bool state)
+{
+    irqEnable = state;
+    DPRINTF(GIC, " Enabling Irq\n");
+    updateIntState(-1);
+}
+
+void
+Gic::driveLegIRQ(bool state)
+{
+    if (irqEnable && !(!enabled && cpuEnabled[0])) {
+        if (state) {
+            DPRINTF(GIC, "Driving Legacy Irq\n");
+            platform->intrctrl->post(0, MipsISA::IT_HARD_INT0, 0);
+        }
+        else platform->intrctrl->clear(0, MipsISA::IT_HARD_INT0, 0);
+    }
+}
+
+void
+Gic::driveLegFIQ(bool state)
+{
+    if (state)
+        platform->intrctrl->post(0, MipsISA::IT_HARD_INT0, 0);
+    else platform->intrctrl->clear(0, MipsISA::IT_HARD_INT0, 0);
+}
diff -r f348cf78072c src/dev/mips/pl011.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/pl011.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+
+/** @file
+ * Implementiation of a PL011 UART
+ */
+
+#ifndef __DEV_ARM_PL011_H__
+#define __DEV_ARM_PL011_H__
+
+#include "base/range.hh"
+#include "dev/io_device.hh"
+#include "dev/uart.hh"
+#include "params/Pl011.hh"
+
+class Gic;
+
+class Pl011 : public Uart
+{
+  protected:
+    static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
+    static const int UART_DR = 0x000;
+    static const int UART_FR = 0x018;
+    static const int UART_FR_CTS  = 0x001;
+    static const int UART_FR_TXFE = 0x080;
+    static const int UART_FR_RXFE = 0x010;
+    static const int UART_IBRD = 0x024;
+    static const int UART_FBRD = 0x028;
+    static const int UART_LCRH = 0x02C;
+    static const int UART_CR   = 0x030;
+    static const int UART_IFLS = 0x034;
+    static const int UART_IMSC = 0x038;
+    static const int UART_RIS  = 0x03C;
+    static const int UART_MIS  = 0x040;
+    static const int UART_ICR  = 0x044;
+
+    uint16_t control;
+
+    /** fractional baud rate divisor. Not used for anything but reporting
+     * written value */
+    uint16_t fbrd;
+
+    /** integer baud rate divisor. Not used for anything but reporting
+     * written value */
+    uint16_t ibrd;
+
+    /** Line control register. Not used for anything but reporting
+     * written value */
+    uint16_t lcrh;
+
+    /** interrupt fifo level register. Not used for anything but reporting
+     * written value */
+    uint16_t ifls;
+
+    BitUnion16(INTREG)
+        Bitfield<0> rimim;
+        Bitfield<1> ctsmim;
+        Bitfield<2> dcdmim;
+        Bitfield<3> dsrmim;
+        Bitfield<4> rxim;
+        Bitfield<5> txim;
+        Bitfield<6> rtim;
+        Bitfield<7> feim;
+        Bitfield<8> peim;
+        Bitfield<9> beim;
+        Bitfield<10> oeim;
+        Bitfield<15,11> rsvd;
+    EndBitUnion(INTREG)
+
+    /** interrupt mask register. */
+    INTREG imsc;
+
+    /** raw interrupt status register */
+    INTREG rawInt;
+
+    /** Masked interrupt status register */
+    INTREG maskInt;
+
+    /** Interrupt number to generate */
+    int intNum;
+
+    /** Gic to use for interrupting */
+    Gic *gic;
+
+    /** Should the simulation end on an EOT */
+    bool endOnEOT;
+
+    /** Delay before interrupting */
+    Tick intDelay;
+
+    /** Function to generate interrupt */
+    void generateInterrupt();
+
+    /** Wrapper to create an event out of the thing */
+    EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
+
+  public:
+   typedef Pl011Params Params;
+   const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+    Pl011(const Params *p);
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
+
+    /**
+     * Inform the uart that there is data available.
+     */
+    virtual void dataAvailable();
+
+
+    /**
+     * Return if we have an interrupt pending
+     * @return interrupt status
+     * @todo fix me when implementation improves
+     */
+    virtual bool intStatus() { return false; }
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+};
+
+#endif //__DEV_ARM_PL011_H__
diff -r f348cf78072c src/dev/mips/pl011.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/pl011.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "base/trace.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/Uart.hh"
+#include "dev/mips/amba_device.hh"
+#include "dev/mips/gic.hh"
+#include "dev/mips/pl011.hh"
+#include "dev/terminal.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "sim/sim_exit.hh"
+
+Pl011::Pl011(const Params *p)
+    : Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0),
+      rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic),
+      endOnEOT(p->end_on_eot), intDelay(p->int_delay), intEvent(this)
+{
+    pioSize = 0xfff;
+}
+
+Tick
+Pl011::read(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+
+    Addr daddr = pkt->getAddr() - pioAddr;
+    pkt->allocate();
+
+    DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
+
+    // use a temporary data since the uart registers are read/written with
+    // different size operations
+    //
+    uint32_t data = 0;
+
+    switch(daddr) {
+      case UART_DR:
+        data = 0;
+        if (term->dataAvailable())
+            data = term->in();
+        break;
+      case UART_FR:
+        // For now we're infintely fast, so TX is never full, always empty,
+        // always clear to send
+        data = UART_FR_TXFE | UART_FR_CTS;
+        if (!term->dataAvailable())
+            data |= UART_FR_RXFE;
+        DPRINTF(Uart, "Reading FR register as %#x rawInt=0x%x imsc=0x%x maskInt=0x%x\n",
+                data, rawInt, imsc, maskInt);
+        break;
+      case UART_CR:
+        data = control;
+        break;
+      case UART_IBRD:
+        data = ibrd;
+        break;
+      case UART_FBRD:
+        data = fbrd;
+        break;
+      case UART_LCRH:
+        data = lcrh;
+        break;
+      case UART_IFLS:
+        data = ifls;
+        break;
+      case UART_IMSC:
+        data = imsc;
+        break;
+      case UART_RIS:
+        data = rawInt;
+        DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
+        break;
+      case UART_MIS:
+        DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", rawInt);
+        data = maskInt;
+        break;
+      default:
+        if (AmbaDev::readId(pkt, AMBA_ID, pioAddr)) {
+            // Hack for variable size accesses
+            data = pkt->get<uint32_t>();
+            break;
+        }
+
+        panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
+        break;
+    }
+
+    switch(pkt->getSize()) {
+      case 1:
+        pkt->set<uint8_t>(data);
+        break;
+      case 2:
+        pkt->set<uint16_t>(data);
+        break;
+      case 4:
+        pkt->set<uint32_t>(data);
+        break;
+      default:
+        panic("Uart read size too big?\n");
+        break;
+    }
+
+
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+Tick
+Pl011::write(PacketPtr pkt)
+{
+
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+
+    Addr daddr = pkt->getAddr() - pioAddr;
+
+    DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
+            pkt->get<uint8_t>(), pkt->getSize());
+
+    // use a temporary data since the uart registers are read/written with
+    // different size operations
+    //
+    uint32_t data = 0;
+
+    switch(pkt->getSize()) {
+      case 1:
+        data = pkt->get<uint8_t>();
+        break;
+      case 2:
+        data = pkt->get<uint16_t>();
+        break;
+      case 4:
+        data = pkt->get<uint32_t>();
+        break;
+      default:
+        panic("Uart write size too big?\n");
+        break;
+    }
+
+
+    switch (daddr) {
+        case UART_DR:
+          if ((data & 0xFF) == 0x04 && endOnEOT)
+            exitSimLoop("UART received EOT", 0);
+
+        term->out(data & 0xFF);
+
+        if (imsc.txim) {
+            DPRINTF(Uart, "TX int enabled, scheduling interruptt\n");
+            rawInt.txim = 1;
+            if (!intEvent.scheduled())
+                schedule(intEvent, curTick() + intDelay);
+        }
+
+        break;
+      case UART_CR:
+        control = data;
+        break;
+      case UART_IBRD:
+        ibrd = data;
+        break;
+      case UART_FBRD:
+        fbrd = data;
+        break;
+      case UART_LCRH:
+        lcrh = data;
+        break;
+      case UART_IFLS:
+        ifls = data;
+        break;
+      case UART_IMSC:
+        imsc = data;
+
+        if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim
+             || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd)
+            panic("Unknown interrupt enabled\n");
+
+        if (imsc.txim) {
+            DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n");
+            rawInt.txim = 1;
+            if (!intEvent.scheduled())
+                schedule(intEvent, curTick() + intDelay);
+        }
+
+        break;
+
+      case UART_ICR:
+        DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
+        rawInt = rawInt & ~data;
+        maskInt = rawInt & imsc;
+
+        DPRINTF(Uart, " -- Masked interrupts 0x%x\n", maskInt);
+
+        if (!maskInt)
+            gic->clearInt(intNum);
+
+        break;
+      default:
+        panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
+        break;
+    }
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+void
+Pl011::dataAvailable()
+{
+    /*@todo ignore the fifo, just say we have data now
+     * We might want to fix this, or we might not care */
+    rawInt.rxim = 1;
+    rawInt.rtim = 1;
+
+    DPRINTF(Uart, "Data available, scheduling interrupt\n");
+
+    if (!intEvent.scheduled())
+        schedule(intEvent, curTick() + intDelay);
+}
+
+void
+Pl011::generateInterrupt()
+{
+    DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
+            imsc, rawInt, maskInt);
+    maskInt = imsc & rawInt;
+
+    if (maskInt.rxim || maskInt.rtim || maskInt.txim) {
+        gic->sendInt(intNum);
+        DPRINTF(Uart, " -- Generated\n");
+    }
+
+}
+
+
+
+void
+Pl011::serialize(std::ostream &os)
+{
+    DPRINTF(Checkpoint, "Serializing Arm PL011\n");
+    SERIALIZE_SCALAR(control);
+    SERIALIZE_SCALAR(fbrd);
+    SERIALIZE_SCALAR(ibrd);
+    SERIALIZE_SCALAR(lcrh);
+    SERIALIZE_SCALAR(ifls);
+
+    uint16_t imsc_serial = imsc;
+    SERIALIZE_SCALAR(imsc_serial);
+
+    uint16_t rawInt_serial = rawInt;
+    SERIALIZE_SCALAR(rawInt_serial);
+
+    uint16_t maskInt_serial = maskInt;
+    SERIALIZE_SCALAR(maskInt_serial);
+
+    SERIALIZE_SCALAR(endOnEOT);
+    SERIALIZE_SCALAR(intDelay);
+}
+
+void
+Pl011::unserialize(Checkpoint *cp, const std::string &section)
+{
+    DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
+
+    UNSERIALIZE_SCALAR(control);
+    UNSERIALIZE_SCALAR(fbrd);
+    UNSERIALIZE_SCALAR(ibrd);
+    UNSERIALIZE_SCALAR(lcrh);
+    UNSERIALIZE_SCALAR(ifls);
+
+    uint16_t imsc_serial;
+    UNSERIALIZE_SCALAR(imsc_serial);
+    imsc = imsc_serial;
+
+    uint16_t rawInt_serial;
+    UNSERIALIZE_SCALAR(rawInt_serial);
+    rawInt = rawInt_serial;
+
+    uint16_t maskInt_serial;
+    UNSERIALIZE_SCALAR(maskInt_serial);
+    maskInt = maskInt_serial;
+
+    UNSERIALIZE_SCALAR(endOnEOT);
+    UNSERIALIZE_SCALAR(intDelay);
+}
+
+Pl011 *
+Pl011Params::create()
+{
+    return new Pl011(this);
+}
diff -r f348cf78072c src/dev/mips/realview.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/realview.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2009 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/**
+ * @file
+ * Declaration of top level class for the RealView platform chips. This class just
+ * retains pointers to all its children so the children can communicate.
+ */
+
+#ifndef __DEV_ARM_RealView_HH__
+#define __DEV_ARM_RealView_HH__
+
+#include "dev/platform.hh"
+#include "params/RealView.hh"
+
+class IdeController;
+class System;
+
+class RealView : public Platform
+{
+  public:
+    /** Pointer to the system */
+    System *system;
+
+  public:
+    typedef RealViewParams Params;
+    /**
+     * Constructor for the Tsunami Class.
+     * @param name name of the object
+     * @param s system the object belongs to
+     * @param intctrl pointer to the interrupt controller
+     */
+    RealView(const Params *p);
+
+    /**
+     * Return the interrupting frequency to AlphaAccess
+     * @return frequency of RTC interrupts
+     */
+    virtual Tick intrFrequency();
+
+    /**
+     * Cause the cpu to post a serial interrupt to the CPU.
+     */
+    virtual void postConsoleInt();
+
+    /**
+     * Clear a posted CPU interrupt
+     */
+    virtual void clearConsoleInt();
+
+    /**
+     * Cause the chipset to post a cpi interrupt to the CPU.
+     */
+    virtual void postPciInt(int line);
+
+    /**
+     * Clear a posted PCI->CPU interrupt
+     */
+    virtual void clearPciInt(int line);
+
+
+    virtual Addr pciToDma(Addr pciAddr) const;
+
+    /**
+     * Calculate the configuration address given a bus/dev/func.
+     */
+    virtual Addr calcPciConfigAddr(int bus, int dev, int func);
+
+    /**
+     * Calculate the address for an IO location on the PCI bus.
+     */
+    virtual Addr calcPciIOAddr(Addr addr);
+
+    /**
+     * Calculate the address for a memory location on the PCI bus.
+     */
+    virtual Addr calcPciMemAddr(Addr addr);
+};
+
+#endif // __DEV_ARM_RealView_HH__
diff -r f348cf78072c src/dev/mips/realview.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/realview.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2009 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Implementation of RealView platform.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "config/the_isa.hh"
+#include "cpu/intr_control.hh"
+#include "dev/mips/realview.hh"
+#include "dev/terminal.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace TheISA;
+
+RealView::RealView(const Params *p)
+    : Platform(p), system(p->system)
+{
+    // set the back pointer from the system to myself
+    system->platform = this;
+}
+
+Tick
+RealView::intrFrequency()
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+void
+RealView::postConsoleInt()
+{
+    warn_once("Don't know what interrupt to post for console.\n");
+    //panic("Need implementation\n");
+}
+
+void
+RealView::clearConsoleInt()
+{
+    warn_once("Don't know what interrupt to clear for console.\n");
+    //panic("Need implementation\n");
+}
+
+void
+RealView::postPciInt(int line)
+{
+    panic("Need implementation\n");
+}
+
+void
+RealView::clearPciInt(int line)
+{
+    panic("Need implementation\n");
+}
+
+Addr
+RealView::pciToDma(Addr pciAddr) const
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+
+Addr
+RealView::calcPciConfigAddr(int bus, int dev, int func)
+{
+    return ULL(-1);
+}
+
+Addr
+RealView::calcPciIOAddr(Addr addr)
+{
+    return addr;
+}
+
+Addr
+RealView::calcPciMemAddr(Addr addr)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+RealView *
+RealViewParams::create()
+{
+    return new RealView(this);
+}
diff -r f348cf78072c src/dev/mips/rv_ctrl.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/rv_ctrl.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __DEV_ARM_RV_HH__
+#define __DEV_ARM_RV_HH__
+
+#include "base/bitunion.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
+#include "params/RealViewCtrl.hh"
+
+/** @file
+ * This implements the simple real view registers on a PBXA9
+ */
+
+class RealViewCtrl : public BasicPioDevice
+{
+  protected:
+    enum {
+        IdReg      = 0x00,
+        SwReg      = 0x04,
+        Led        = 0x08,
+        Osc0       = 0x0C,
+        Osc1       = 0x10,
+        Osc2       = 0x14,
+        Osc3       = 0x18,
+        Osc4       = 0x1C,
+        Lock       = 0x20,
+        Clock100   = 0x24,
+        CfgData1   = 0x28,
+        CfgData2   = 0x2C,
+        Flags      = 0x30,
+        FlagsClr   = 0x34,
+        NvFlags    = 0x38,
+        NvFlagsClr = 0x3C,
+        ResetCtl   = 0x40,
+        PciCtl     = 0x44,
+        MciCtl     = 0x48,
+        Flash      = 0x4C,
+        Clcd       = 0x50,
+        ClcdSer    = 0x54,
+        Bootcs     = 0x58,
+        Clock24    = 0x5C,
+        Misc       = 0x60,
+        IoSel      = 0x70,
+        ProcId     = 0x84,
+        TestOsc0   = 0xC0,
+        TestOsc1   = 0xC4,
+        TestOsc2   = 0xC8,
+        TestOsc3   = 0xCC,
+        TestOsc4   = 0xD0
+    };
+
+    // system lock value
+    BitUnion32(SysLockReg)
+        Bitfield<15,0> lockVal;
+        Bitfield<16> locked;
+    EndBitUnion(SysLockReg)
+
+    SysLockReg sysLock;
+
+    /** This register is used for smp booting.
+     * The primary cpu writes the secondary start address here before
+     * sends it a soft interrupt. The secondary cpu reads this register and if
+     * it's non-zero it jumps to the address
+     */
+    uint32_t flags;
+
+  public:
+    typedef RealViewCtrlParams Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+    /**
+      * The constructor for RealView just registers itself with the MMU.
+      * @param p params structure
+      */
+    RealViewCtrl(Params *p);
+
+    /**
+     * Handle a read to the device
+     * @param pkt The memory request.
+     * @param data Where to put the data.
+     */
+    virtual Tick read(PacketPtr pkt);
+
+    /**
+     * All writes are simply ignored.
+     * @param pkt The memory request.
+     * @param data the data
+     */
+    virtual Tick write(PacketPtr pkt);
+
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+
+#endif // __DEV_ARM_RV_HH__
diff -r f348cf78072c src/dev/mips/rv_ctrl.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/rv_ctrl.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "base/trace.hh"
+#include "dev/mips/rv_ctrl.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+RealViewCtrl::RealViewCtrl(Params *p)
+    : BasicPioDevice(p), flags(0)
+{
+    pioSize = 0xD4;
+}
+
+Tick
+RealViewCtrl::read(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    assert(pkt->getSize() == 4);
+    Addr daddr = pkt->getAddr() - pioAddr;
+    pkt->allocate();
+
+    switch(daddr) {
+      case ProcId:
+        pkt->set(params()->proc_id);
+        break;
+      case Clock24:
+        Tick clk;
+        clk = (Tick)(curTick() / (24 * SimClock::Int::us));
+        pkt->set((uint32_t)(clk));
+        break;
+      case Clock100:
+        Tick clk100;
+        clk100 = (Tick)(curTick() / (100 * SimClock::Int::us));
+        pkt->set((uint32_t)(clk100));
+        break;
+      case Flash:
+        pkt->set<uint32_t>(0);
+        break;
+      case Clcd:
+        pkt->set<uint32_t>(0x00001F00);
+        break;
+      case Osc0:
+        pkt->set<uint32_t>(0x00012C5C);
+        break;
+      case Osc1:
+        pkt->set<uint32_t>(0x00002CC0);
+        break;
+      case Osc2:
+        pkt->set<uint32_t>(0x00002C75);
+        break;
+      case Osc3:
+        pkt->set<uint32_t>(0x00020211);
+        break;
+      case Osc4:
+        pkt->set<uint32_t>(0x00002C75);
+        break;
+      case Lock:
+        pkt->set<uint32_t>(sysLock);
+        break;
+      case Flags:
+        pkt->set<uint32_t>(flags);
+        break;
+      case IdReg:
+        pkt->set<uint32_t>(params()->idreg);
+        break;
+      default:
+        warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
+             daddr);
+        break;
+    }
+    pkt->makeAtomicResponse();
+    return pioDelay;
+
+}
+
+Tick
+RealViewCtrl::write(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+
+    Addr daddr = pkt->getAddr() - pioAddr;
+    switch (daddr) {
+      case Flash:
+      case Clcd:
+      case Osc0:
+      case Osc1:
+      case Osc2:
+      case Osc3:
+      case Osc4:
+        break;
+      case Lock:
+        sysLock.lockVal = pkt->get<uint16_t>();
+        break;
+      case Flags:
+        flags = pkt->get<uint32_t>();
+        break;
+      default:
+        warn("Tried to write RVIO at offset %#x that doesn't exist\n",
+             daddr);
+        break;
+    }
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+void
+RealViewCtrl::serialize(std::ostream &os)
+{
+    SERIALIZE_SCALAR(flags);
+}
+
+void
+RealViewCtrl::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_SCALAR(flags);
+}
+
+RealViewCtrl *
+RealViewCtrlParams::create()
+{
+    return new RealViewCtrl(this);
+}
diff -r f348cf78072c src/dev/mips/timer_sp804.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/timer_sp804.hh	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __DEV_ARM_SP804_HH__
+#define __DEV_ARM_SP804_HH__
+
+#include "base/range.hh"
+#include "dev/mips/amba_device.hh"
+#include "params/Sp804.hh"
+
+/** @file
+ * This implements the dual Sp804 timer block
+ */
+
+class Gic;
+
+class Sp804 : public AmbaDevice
+{
+  protected:
+    class Timer
+    {
+
+      public:
+        enum {
+            LoadReg    = 0x00,
+            CurrentReg = 0x04,
+            ControlReg = 0x08,
+            IntClear   = 0x0C,
+            RawISR     = 0x10,
+            MaskedISR  = 0x14,
+            BGLoad     = 0x18,
+            Size       = 0x20
+        };
+
+        BitUnion32(CTRL)
+            Bitfield<0>   oneShot;
+            Bitfield<1>   timerSize;
+            Bitfield<3,2> timerPrescale;
+            Bitfield<5>   intEnable;
+            Bitfield<6>   timerMode;
+            Bitfield<7>   timerEnable;
+        EndBitUnion(CTRL)
+
+      protected:
+        std::string _name;
+
+        /** Pointer to parent class */
+        Sp804 *parent;
+
+        /** Number of interrupt to cause/clear */
+        uint32_t intNum;
+
+        /** Number of ticks in a clock input */
+        Tick clock;
+
+        /** Control register as specified above */
+        CTRL control;
+
+        /** If timer has caused an interrupt. This is irrespective of
+         * interrupt enable */
+        bool rawInt;
+
+        /** If an interrupt is currently pending. Logical and of CTRL.intEnable
+         * and rawInt */
+        bool pendingInt;
+
+        /** Value to load into counter when periodic mode reaches 0 */
+        uint32_t loadValue;
+
+        /** Called when the counter reaches 0 */
+        void counterAtZero();
+        EventWrapper<Timer, &Timer::counterAtZero> zeroEvent;
+
+      public:
+        /** Restart the counter ticking at val
+         * @param val the value to start at (pre-16 bit masking if en) */
+        void restartCounter(uint32_t val);
+
+        Timer(std::string __name, Sp804 *parent, int int_num, Tick clock);
+
+        std::string name() const { return _name; }
+
+        /** Handle read for a single timer */
+        void read(PacketPtr pkt, Addr daddr);
+
+        /** Handle write for a single timer */
+        void write(PacketPtr pkt, Addr daddr);
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+    };
+
+    /** Pointer to the GIC for causing an interrupt */
+    Gic *gic;
+
+    /** Timers that do the actual work */
+    Timer timer0;
+    Timer timer1;
+
+  public:
+    typedef Sp804Params Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+    /**
+      * The constructor for RealView just registers itself with the MMU.
+      * @param p params structure
+      */
+    Sp804(Params *p);
+
+    /**
+     * Handle a read to the device
+     * @param pkt The memory request.
+     * @param data Where to put the data.
+     */
+    virtual Tick read(PacketPtr pkt);
+
+    /**
+     * All writes are simply ignored.
+     * @param pkt The memory request.
+     * @param data the data
+     */
+    virtual Tick write(PacketPtr pkt);
+
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+
+#endif // __DEV_ARM_SP804_HH__
+
diff -r f348cf78072c src/dev/mips/timer_sp804.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/mips/timer_sp804.cc	Fri Jan 13 03:22:43 2012 +0800
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "base/intmath.hh"
+#include "base/trace.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/Timer.hh"
+#include "dev/mips/gic.hh"
+#include "dev/mips/timer_sp804.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+using namespace AmbaDev;
+
+Sp804::Sp804(Params *p)
+    : AmbaDevice(p), gic(p->gic), timer0(name() + ".timer0", this, p->int_num0, p->clock0),
+      timer1(name() + ".timer1", this, p->int_num1, p->clock1)
+{
+    pioSize = 0xfff;
+}
+
+Sp804::Timer::Timer(std::string __name, Sp804 *_parent, int int_num, Tick _clock)
+    : _name(__name), parent(_parent), intNum(int_num), clock(_clock), control(0x20),
+      rawInt(false), pendingInt(false), loadValue(0xffffffff), zeroEvent(this)
+{
+}
+
+
+Tick
+Sp804::read(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    assert(pkt->getSize() == 4);
+    Addr daddr = pkt->getAddr() - pioAddr;
+    pkt->allocate();
+    DPRINTF(Timer, "Reading from DualTimer at offset: %#x\n", daddr);
+
+    if (daddr < Timer::Size)
+        timer0.read(pkt, daddr);
+    else if ((daddr - Timer::Size) < Timer::Size)
+        timer1.read(pkt, daddr - Timer::Size);
+    else if (!readId(pkt, ambaId, pioAddr))
+        panic("Tried to read SP804 at offset %#x that doesn't exist\n", daddr);
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+
+void
+Sp804::Timer::read(PacketPtr pkt, Addr daddr)
+{
+    switch(daddr) {
+      case LoadReg:
+        pkt->set<uint32_t>(loadValue);
+        break;
+      case CurrentReg:
+        DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
+                zeroEvent.when(), clock, control.timerPrescale);
+        Tick time;
+        time = zeroEvent.when() - curTick();
+        time = time / clock / power(16, control.timerPrescale);
+        DPRINTF(Timer, "-- returning counter at %d\n", time);
+        pkt->set<uint32_t>(time);
+        break;
+      case ControlReg:
+        pkt->set<uint32_t>(control);
+        break;
+      case RawISR:
+        pkt->set<uint32_t>(rawInt);
+        break;
+      case MaskedISR:
+        pkt->set<uint32_t>(pendingInt);
+        break;
+      case BGLoad:
+        pkt->set<uint32_t>(loadValue);
+        break;
+      default:
+        panic("Tried to read SP804 timer at offset %#x\n", daddr);
+        break;
+    }
+    DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr);
+}
+
+Tick
+Sp804::write(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    assert(pkt->getSize() == 4);
+    Addr daddr = pkt->getAddr() - pioAddr;
+    pkt->allocate();
+    DPRINTF(Timer, "Writing to DualTimer at offset: %#x\n", daddr);
+
+    if (daddr < Timer::Size)
+        timer0.write(pkt, daddr);
+    else if ((daddr - Timer::Size) < Timer::Size)
+        timer1.write(pkt, daddr - Timer::Size);
+    else if (!readId(pkt, ambaId, pioAddr))
+        panic("Tried to write SP804 at offset %#x that doesn't exist\n", daddr);
+    pkt->makeAtomicResponse();
+    return pioDelay;
+}
+
+void
+Sp804::Timer::write(PacketPtr pkt, Addr daddr)
+{
+    DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr);
+    switch (daddr) {
+      case LoadReg:
+        loadValue = pkt->get<uint32_t>();
+        restartCounter(loadValue);
+        break;
+      case CurrentReg:
+        // Spec says this value can't be written, but linux writes it anyway
+        break;
+      case ControlReg:
+        bool old_enable;
+        old_enable = control.timerEnable;
+        control = pkt->get<uint32_t>();
+        if ((old_enable == 0) && control.timerEnable)
+            restartCounter(loadValue);
+        break;
+      case IntClear:
+        rawInt = false;
+        if (pendingInt) {
+            pendingInt = false;
+            DPRINTF(Timer, "Clearing interrupt\n");
+            parent->gic->clearInt(intNum);
+        }
+        break;
+      case BGLoad:
+        loadValue = pkt->get<uint32_t>();
+        break;
+      default:
+        panic("Tried to write SP804 timer at offset %#x\n", daddr);
+        break;
+    }
+}
+
+void
+Sp804::Timer::restartCounter(uint32_t val)
+{
+    DPRINTF(Timer, "Resetting counter with value %#x\n", val);
+    if (!control.timerEnable)
+        return;
+
+    Tick time = clock * power(16, control.timerPrescale);
+    if (control.timerSize)
+        time *= val;
+    else
+        time *= bits(val,15,0);
+
+    if (zeroEvent.scheduled()) {
+        DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
+        parent->deschedule(zeroEvent);
+    }
+    parent->schedule(zeroEvent, curTick() + time);
+    DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
+}
+
+void
+Sp804::Timer::counterAtZero()
+{
+    if (!control.timerEnable)
+        return;
+
+    DPRINTF(Timer, "Counter reached zero\n");
+
+    rawInt = true;
+    bool old_pending = pendingInt;
+    if (control.intEnable)
+        pendingInt = true;
+    if (pendingInt && ~old_pending) {
+        DPRINTF(Timer, "-- Causing interrupt\n");
+        parent->gic->sendInt(intNum);
+    }
+
+    if (control.oneShot)
+        return;
+
+    // Free-running
+    if (control.timerMode == 0)
+        restartCounter(0xffffffff);
+    else
+        restartCounter(loadValue);
+}
+
+void
+Sp804::Timer::serialize(std::ostream &os)
+{
+    DPRINTF(Checkpoint, "Serializing Arm Sp804\n");
+    SERIALIZE_SCALAR(intNum);
+    SERIALIZE_SCALAR(clock);
+
+    uint32_t control_serial = control;
+    SERIALIZE_SCALAR(control_serial);
+
+    SERIALIZE_SCALAR(rawInt);
+    SERIALIZE_SCALAR(pendingInt);
+    SERIALIZE_SCALAR(loadValue);
+
+    bool is_in_event = zeroEvent.scheduled();
+    SERIALIZE_SCALAR(is_in_event);
+
+    Tick event_time;
+    if (is_in_event){
+        event_time = zeroEvent.when();
+        SERIALIZE_SCALAR(event_time);
+    }
+}
+
+void
+Sp804::Timer::unserialize(Checkpoint *cp, const std::string &section)
+{
+    DPRINTF(Checkpoint, "Unserializing Arm Sp804\n");
+
+    UNSERIALIZE_SCALAR(intNum);
+    UNSERIALIZE_SCALAR(clock);
+
+    uint32_t control_serial;
+    UNSERIALIZE_SCALAR(control_serial);
+    control = control_serial;
+
+    UNSERIALIZE_SCALAR(rawInt);
+    UNSERIALIZE_SCALAR(pendingInt);
+    UNSERIALIZE_SCALAR(loadValue);
+
+    bool is_in_event;
+    UNSERIALIZE_SCALAR(is_in_event);
+
+    Tick event_time;
+    if (is_in_event){
+        UNSERIALIZE_SCALAR(event_time);
+        parent->schedule(zeroEvent, event_time);
+    }
+}
+
+
+
+void
+Sp804::serialize(std::ostream &os)
+{
+    nameOut(os, csprintf("%s.timer0", name()));
+    timer0.serialize(os);
+    nameOut(os, csprintf("%s.timer1", name()));
+    timer1.serialize(os);
+}
+
+void
+Sp804::unserialize(Checkpoint *cp, const std::string &section)
+{
+    timer0.unserialize(cp, csprintf("%s.timer0", section));
+    timer1.unserialize(cp, csprintf("%s.timer1", section));
+}
+
+Sp804 *
+Sp804Params::create()
+{
+    return new Sp804(this);
+}