diff -r f348cf78072c configs/example/fs.py
--- a/configs/example/fs.py	Thu Jan 12 10:15:00 2012 -0500
+++ b/configs/example/fs.py	Tue Jan 17 00:34:42 2012 +0800
@@ -179,9 +179,6 @@
     if options.fastmem:
         test_sys.cpu[i].physmem_port = test_sys.physmem.port
 
-if buildEnv['TARGET_ISA'] == 'mips':
-    setMipsOptions(TestCPUClass)
-
 if len(bm) == 2:
     if buildEnv['TARGET_ISA'] == 'alpha':
         drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
diff -r f348cf78072c src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc	Thu Jan 12 10:15:00 2012 -0500
+++ b/src/arch/mips/isa.cc	Tue Jan 17 00:34:42 2012 +0800
@@ -152,6 +152,8 @@
         for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
             miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
     }
+
+    configCP();
 }
 
 
@@ -162,9 +164,66 @@
             numThreads, numVpes);
 
     CoreSpecific cp;
-    panic("CP state must be set before the following code is used");
 
     // Do Default CP0 initialization HERE
+    // 1. CP0 Configuration
+    cp.CP0_PRId_CompanyOptions = 0;
+    cp.CP0_PRId_CompanyID = 1;
+    cp.CP0_PRId_ProcessorID = 147;
+    cp.CP0_PRId_Revision = 0;
+
+    // 2. CP0 Interrupt Control
+    cp.CP0_IntCtl_IPTI = 7;
+    cp.CP0_IntCtl_IPPCI = 7;
+
+    // 3. Config Register
+    //cp.CP0_Config_K23 = 0 # Since TLB
+    //cp.CP0_Config_KU = 0 # Since TLB
+    cp.CP0_Config_BE = 0; // Little Endian
+    cp.CP0_Config_AR = 1; // Architecture Revision 2
+    cp.CP0_Config_AT = 0; // MIPS32
+    cp.CP0_Config_MT = 1; // TLB MMU
+    //cp.CP0_Config_K0 = 2; // Uncached
+
+    // 4. Config 1 Register
+    cp.CP0_Config1_M = 1; // Config2 Implemented
+    cp.CP0_Config1_MMU = 63; // TLB Size
+    // ***VERY IMPORTANT***
+    // Remember to modify CP0_Config1 according to cache specs
+    // Examine file ../common/Cache.py
+    cp.CP0_Config1_IS = 1; // I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
+    cp.CP0_Config1_IL = 5; // I-Cache Line Size, default in Cache.py is 64, i.e 5
+    cp.CP0_Config1_IA = 1; // I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
+    cp.CP0_Config1_DS = 2; // D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
+    cp.CP0_Config1_DL = 5; // D-Cache Line Size, default is 64, i.e., 5
+    cp.CP0_Config1_DA = 1; // D-Cache Associativity, default is 2, i.e. 1
+    cp.CP0_Config1_C2 = 0; // Coprocessor 2 not implemented(?)
+    cp.CP0_Config1_MD = 0; // MDMX ASE not implemented in Mips32
+    cp.CP0_Config1_PC = 1; // Performance Counters Implemented
+    cp.CP0_Config1_WR = 0; // Watch Registers Implemented
+    cp.CP0_Config1_CA = 0; // Mips16e NOT implemented
+    cp.CP0_Config1_EP = 0; // EJTag Not Implemented
+    cp.CP0_Config1_FP = 0; // FPU Implemented
+
+    // 5. Config 2 Register
+    cp.CP0_Config2_M =  1; //Config3 Implemented
+    cp.CP0_Config2_TU = 0; //Tertiary Cache Control
+    cp.CP0_Config2_TS = 0; //Tertiary Cache Sets Per Way
+    cp.CP0_Config2_TL = 0; //Tertiary Cache Line Size
+    cp.CP0_Config2_TA = 0; //Tertiary Cache Associativity
+    cp.CP0_Config2_SU = 0; //Secondary Cache Control
+    cp.CP0_Config2_SS = 0; //Secondary Cache Sets Per Way
+    cp.CP0_Config2_SL = 0; //Secondary Cache Line Size
+    cp.CP0_Config2_SA = 0; //Secondary Cache Associativity
+
+    // 6. Config 3 Register
+    cp.CP0_Config3_M = 0;    //Config4 Not Implemented
+    cp.CP0_Config3_DSPP = 1; //DSP ASE Present
+    cp.CP0_Config3_LPA = 0;  //Large Physical Addresses Not supported in Mips32
+    cp.CP0_Config3_VEIC = 0; //EIC Supported
+    cp.CP0_Config3_VInt = 0; //Vectored Interrupts Implemented
+    cp.CP0_Config3_SP = 0;   //Small Pages Supported (PageGrain reg. exists)
+	
 
     // Do Initialization for MT cores here (eventually use
     // core_name parameter to toggle this initialization)