Review Board 2.0.15


Adding TSX support to gem5

Review Request #2308 - Created July 4, 2014 and updated

Information
Pradip Vallathol
gem5
Reviewers
Default
The patch adds (partial) support for TSX instructions in gem5.

Below is the summary of features added:
- 3 new instructions added to X86 ISA: xbegin, xabort and xend
- Added memory level support required by the instructions to the L0 and the L1 cache. L0 cache maintains the transactional state while L1 helps in versioning.
- The O3 CPU model has been modified to support the special transactional requests. Other CPU models are not supported.
- Support for HLE prefixes (XACQUIRE and XRELEASE) have also been provided. Prefixes for all instructions are not yet supported. But the code to generate HLE prefixed instructions has been templatized for easy use.

Acknowledgement:
This work was done as a part of the course Advanced Topics in Computer Architecture at UW-Madison under Prof. David Wood along with Robin Paul Prakash and extended during a Masters Project under Prof. David Wood.

[Resubmitting because first submit failed]
Testing was done using a set of microbenchmarks written during the development phase and also using the STAMP benchmark suite which was modified to use the TSX instructions.
[The microbenchmarks used to test the implementation is attached]
Review request changed
Updated (July 4, 2014, 8:20 p.m.)

Change Summary:

[Resubmitting since the first submit was rejected.]

Description:

   

The patch adds (partial) support for TSX instructions in gem5.

   
   

Below is the summary of features added:

    - 3 new instructions added to X86 ISA: xbegin, xabort and xend
    - Added memory level support required by the instructions to the L0 and the L1 cache. L0 cache maintains the transactional state while L1 helps in versioning.
    - The O3 CPU model has been modified to support the special transactional requests. Other CPU models are not supported.
    - Support for HLE prefixes (XACQUIRE and XRELEASE) have also been provided. Prefixes for all instructions are not yet supported. But the code to generate HLE prefixed instructions has been templatized for easy use.

   
   

Acknowledgement:

    This work was done as a part of the course Advanced Topics in Computer Architecture at UW-Madison under Prof. David Wood along with Robin Paul Prakash and extended during a Masters Project under Prof. David Wood.

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[Resubmitting because first submit failed]

Posted (Aug. 16, 2014, 9:37 a.m.)
Pradip, several comments.

* If possible, split this patch into smaller ones.
* Drop the code that has been commented out.  
* If possible, do not add a new protocol.  Modify the existing one
so that it works with and without TSX as well.