Review Board 2.0.15


  • Joel Hestness

    jthestness

    Joel Hestness
    Last logged in Jan. 24, 2017
    Joined July 21, 2010
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jthestness's review requests

Summary Submitter Posted Last Updated
ruby: PerfectSwitch add assured access arbitration
jthestness
December 23rd, 2016, 2:56 p.m.
sim: Fix SE mode checkpoint restore file handling
jthestness
August 29th, 2015, 4:24 p.m.
ruby: Make MessageBuffers actually finite sized
jthestness
January 17th, 2016, 4:40 p.m.
ruby: Add occupancy stats to MessageBuffers
jthestness
January 23rd, 2016, 8:59 p.m.
ruby: Fix block_on behavior
jthestness
October 9th, 2015, 3:15 p.m.
mem: [DRAFT] Make DRAMCtrl response queue finite
jthestness
February 8th, 2016, 7:58 p.m.
ruby: [DRAFT] Finite dir <-> mem buffering and flow-control
jthestness
February 11th, 2016, 10:45 p.m.
ruby: [DRAFT] MOESI_hammer dir<->mem flow-control
jthestness
February 11th, 2016, 10:44 p.m.
mem: Trigger DRAMCtrl resp queue panic
jthestness
February 2nd, 2016, 1:08 a.m.
sim: Don't quiesce UDelayEvents with 0 latency
jthestness
August 28th, 2015, 7:33 p.m.
ruby: Fix memory leak in AbstractController
jthestness
September 2nd, 2015, 1:46 p.m.
ruby: RubyMemoryControl delete requests
jthestness
September 16th, 2015, 6:07 p.m.
syscall_emul: Bandage readlink /proc/self/exe
jthestness
September 13th, 2015, 12:33 a.m.
ruby: RubyPort delete snoop requests
jthestness
September 16th, 2015, 6:06 p.m.
arch, x86: Delete packet in IntDevice::recvResponse
jthestness
September 16th, 2015, 6:07 p.m.
ruby: Fix CacheMemory allocate leak
jthestness
September 2nd, 2015, 1:46 p.m.
ruby: Protocol changes for SimObject MessageBuffers
jthestness
May 25th, 2015, 11:52 p.m.
ruby: Expose MessageBuffers as SimObjects
jthestness
May 25th, 2015, 11:51 p.m.
ruby: Remove the RubyCache/CacheMemory latency
jthestness
May 21st, 2015, 4:05 p.m.
ruby: Change PerfectCacheMemory::lookup to return pointer
jthestness
May 29th, 2015, 2:47 p.m.
ruby: slicc: Dynamically find+declare all MachineTypes
jthestness
May 9th, 2015, 7:29 p.m.
ruby: Fix RubySystem warm-up and cool-down scope
jthestness
April 15th, 2015, 4:40 p.m.
syscall emulation: Return correct writev value
jthestness
December 23rd, 2014, 2:51 p.m.
sim: More rigorous clocking comments
jthestness
June 7th, 2014, 10:02 p.m.
Util: Do not style check symlinks
jthestness
June 7th, 2014, 10 p.m.
config: Initialize and check cpt_starttick
jthestness
August 2nd, 2013, 8:30 p.m.
cpu: Dynamically instantiate O3 CPU LSQUnits
jthestness
July 19th, 2013, 5:35 p.m.
ruby: Fix Topology throttle connections
jthestness
June 30th, 2013, 5:47 p.m.
Configs: Fix up maxtick and maxtime
jthestness
April 7th, 2013, 8:42 p.m.
Ruby Controllers: Order profilers based on version
jthestness
January 19th, 2013, 2:17 p.m.
Simulation.py: Fix handling of maxtick and take_checkpoints
jthestness
April 7th, 2013, 8:42 p.m.
RubyPort: Fix evict/invalidate packet memory leak
jthestness
April 7th, 2013, 8:42 p.m.
[Discarded] Sequencers: Reset clocks after cache warmup/cooldown
jthestness
April 7th, 2013, 8:42 p.m.
Ruby System, Cache Recorder: Use delete [] for trace vars
jthestness
April 5th, 2013, 7:09 p.m.
PacketQueue: Add maxQueueDepth parameter and setter
jthestness
March 17th, 2013, 6:05 p.m.
O3 IEW: Make incrWb and decrWb clearer
jthestness
January 13th, 2013, 3:42 p.m.
RubyPort and Sequencer: Fix draining
jthestness
August 31st, 2012, 4:48 p.m.
Standard Switch: Drain the system before switching CPUs
jthestness
August 31st, 2012, 4:39 p.m.
Base CPU: Initialize profileEvent to NULL
jthestness
August 31st, 2012, 4:18 p.m.
se.py Ruby: Connect TLB walker ports
jthestness
August 31st, 2012, 4:36 p.m.
Ruby Memory Controller: Fix clocking
jthestness
August 21st, 2012, 3:19 p.m.
M5 utility: remove reserve1_func to build for x86
jthestness
August 9th, 2010, 10:15 a.m.
util/m5/m5.c: in readfile(), added memset to touch all pages - ensure they are in the page table
jthestness
July 21st, 2010, 2:55 p.m.
Ruby: remove unused functions in CacheMemory: get/setMemoryValue
jthestness
June 24th, 2011, 1:46 p.m.
TimingCPU: REPOST: Request::NO_ACCESS bypass in completeDataAccess
jthestness
July 28th, 2010, 3:54 p.m.
M5 utility: Touch all pages in readfile buffer
jthestness
August 9th, 2010, 10:16 a.m.
[Discarded] SIMPLE TIMING: when a request is NO_ACCESS (x86 CDA microinstruction), TimingSimpleCPU::completeDataAccess must still complete
jthestness
July 27th, 2010, 3:59 p.m.