MEM: Explicit ports and Python binding on CopyEngine

Information
Submitter:	Andreas Hansson
Repository:	gem5
Branch:	default
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Description

MEM: Explicit ports and Python binding on CopyEngine

The copy-engine ports were previously created implicitly and bound
based on the dma port peer rather than relying on the normal Python
binding (connectPorts) being called explicitly. This patch makes the
copy engine port similar to all other ports in that they are visibly
in the Python class and bound using the normal explicit calls through
Python.

Testing Done

util/regress all passing (disregarding t1000 and eio)

Ship It!

src/dev/CopyEngine.py (Diff revision 1)

Is there only one port?  If so, why not just call it "dma"?  That seems more in line with our standard practice.

Ali Saidi Feb. 2, 2012, 3:23 a.m. (Feb. 2, 2012, 3:23 a.m.)

there are N ports depending on how the dma engine is configured

Steve Reinhardt Feb. 2, 2012, 3:26 a.m. (Feb. 2, 2012, 3:26 a.m.)

Are there N ports with different names, or are you just referring to the fact that it's a VectorPort?

Andreas Hansson Feb. 3, 2012, 1:16 a.m. (Feb. 3, 2012, 1:16 a.m.)

One vertor port called ce_dma or dma, with N elements. I'm happy to change the name, although currently all ports called dma are single element ports. Thoughts?

Steve Reinhardt Feb. 3, 2012, 6:34 a.m. (Feb. 3, 2012, 6:34 a.m.)

I think consistency of having all dma ports being named "dma" trumps trying to distinguish between singleton ports and vector ports via seemingly unrelated changes in naming conventions.

Diff:

Revision 2 (+42 -16)

Show changes

	src/dev/CopyEngine.py
	src/dev/copy_engine.hh
	src/dev/copy_engine.cc

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Status: Closed (submitted)