O3 CPU: Strengthen condition for handling interrupts
Review Request #1018 - Created Jan. 28, 2012 and submitted
| Information | |
|---|---|
| Nilay Vaish | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 8732:75e54d141aa0 --------------------------- O3 CPU: Strengthen condition for handling interrupts The condition for handling interrupts is to check whether or not the cpu's instruction list is empty. As observed, this can lead to cases in which even though the instruction list is empty, interrupts are handled when they should not be. The condition is being strengthened so that interrupts get handled only when the last committed microop did not had IsDelayedCommit set.
Issue Summary
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| Description | From | Last Updated | Status |
|---|---|---|---|
| Is this changing the way interrupts work to interrupt immediately? That is ok, but i would be interesting to know ... | Ali Saidi | Jan. 31, 2012, 2:07 a.m. | Open |
Posted (Jan. 31, 2012, 2:08 a.m.)
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src/cpu/o3/commit_impl.hh (Diff revision 1) -
Is this changing the way interrupts work to interrupt immediately? That is ok, but i would be interesting to know that its changing. If this isn't the case, do we care about if the head instruction is delayed commit because there are more in the pipe.
Posted (Feb. 1, 2012, 12:39 a.m.)
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src/cpu/o3/commit_impl.hh (Diff revision 1) -
Why is there a check for tid == 0 here? Also, where does the Alpha pal-mode check come from? I don't see it in the original code.
