se.py: Changes to ruby portion due to SE/FS merge

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Submitter:	Nilay Vaish
Repository:	gem5
Branch:	default
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Description

Changeset 8895:c19b9e349cd1
---------------------------
se.py: Changes to ruby portion due to SE/FS merge
With the SE/FS merge, interrupt controller is created irrespective of the
mode. This patch creates the interrupt controller when Ruby is used and
connects its ports.

Testing Done

It looks plausible to me, but this isn't my area. I'd recommend a second opinion.

I would suggest to keep it uniform and rely on Ruby if possible. How come we cannot simply use the cpu sequencers master/slave port (they are vector ports)?

Nilay Vaish March 5, 2012, 11:07 p.m. (March 5, 2012, 11:07 p.m.)
```
Andreas, can you ask your question in more detail?
```

Andreas Hansson March 5, 2012, 11:27 p.m. (March 5, 2012, 11:27 p.m.)

Why does it not say:
	
system.cpu[i].createInterruptController()
system.cpu[i].interrupts.pio = system.ruby._cpu_ruby_ports[i].master	
system.cpu[i].interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
system.cpu[i].interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master

Description:

~		Changeset 8880:97c5fbb8d063
	~	Changeset 8895:c19b9e349cd1

		se.py: Changes to ruby portion due to SE/FS merge
		With the SE/FS merge, interrupt controller is created irrespective of the
~		mode. Since interrupts do not go through the Ruby memory system, a separate
~		bus is required for the interrupt controller and the devices. This patch
	~	mode. This patch creates the interrupt controller when Ruby is used and
	~	connects its ports.
-		creates the piobus and the interrupt controller in SE mode for Ruby.

Diff:

Revision 2 (+17 -10)

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configs/example/se.py

Assuming the regressions are happy.

You have a pending review.

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Description:

Changeset 8880:97c5fbb8d063

Changeset 8895:c19b9e349cd1

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Status: Closed (submitted)