inorder: add timing translation
Review Request #1089 - Created March 7, 2012 and discarded
| Information | |
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| Korey Sewell | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
inorder: add timing translation This is Erik Tomusk's patch to add timing translation to InOrder. It's the next step in getting InOrder to work for ARM.
This passes the alpha-hello world regression - Latest update fixed memory leak bug - It also fixes bug that did not correctly handle memory requests that were blocked (the doTLBAccess was always setting the request as completed, however this is not always the case). Latest fixes deadlocks on some alpha, inorder, long regressions (twolf,bzip2,eon). Debug in progress...
Issue Summary
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35
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1
Posted (March 8, 2012, 1:14 a.m.)
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src/cpu/inorder/cpu.cc (Diff revision 3) -
should you still get the fault if it's a prefetch?
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src/cpu/inorder/cpu.cc (Diff revision 3) -
what about doing the access?
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 3) -
probably should delete it then
Posted (March 19, 2012, 3:08 a.m.)
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src/cpu/inorder/cpu.cc (Diff revision 3) -
Can inst be of type InOrderDynInst? Is WholeTranslationState only used on CPUs that use InOrderDynInst?
Review request changed
Updated (March 20, 2012, 5:42 p.m.)
Diff: |
Revision 4 (+223 -50) |
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Posted (March 21, 2012, 1:57 a.m.)
I just about follow what all is happening in this patch. I've made some suggestions to get it to compile.
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src/cpu/inorder/inorder_dyn_inst.hh (Diff revision 4) -
need an #include "cpu/inorder/resources/inorder_translation.hh"
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 4) -
need to pass inst to InOrderTranslationState
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 4) -
should this be: DataTranslation<CacheUnit*> *trans = new DataTranslation<CacheUnit*>(this, inst->state, tid); ?
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 4) -
also need tid and size: ThreadID tid = inst->readTid(); int size = cache_req->dataPkt->getSize();
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 4) -
should this be: memcpy(cache_req->reqData, cache_req->dataPkt->getPtr<uint8_t>(), size); ?
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 4) -
cache_req doesn't have a write_des. What should this do?
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src/cpu/inorder/resources/graduation_unit.cc (Diff revision 4) -
Missing (
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src/cpu/inorder/resources/inorder_translation.hh (Diff revision 4) -
The two bools should be public or have accessor functions
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src/cpu/inorder/resources/inorder_translation.hh (Diff revision 4) -
Also need a DynInstPtr and a CacheReqPtr and corresponding includes. If including CacheUnit, it needs a forward declaration.
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src/cpu/inorder/resources/inorder_translation.hh (Diff revision 4) -
Constructors need to take a DynInstPtr
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src/cpu/inorder/resources/inorder_translation.hh (Diff revision 4) -
also need methods something like: inline bool isRead() { return (mode == BaseTLB::Read); } inline bool isWrite() { return (mode == BaseTLB::Write); } -
src/cpu/translation.hh (Diff revision 4) -
One of the methods here should be virtual to allow for dynamic_cast with InOrderTranslationState
Review request changed
Updated (April 1, 2012, 10:55 a.m.)
Diff: |
Revision 5 (+239 -49) |
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Posted (April 3, 2012, 2:40 p.m.)
Just a quick pass since I didn't want to dig too much into the actual logic of the change.
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src/cpu/inorder/cpu.hh (Diff revision 5) -
This should be included where it's needed, not here. I'm assuming it isn't needed here because it wasn't here before and this code compiled.
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src/cpu/inorder/cpu.cc (Diff revision 5) -
This file isn't actually different. Please remove it from the change.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Unnecessary white space change.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Why is this part of the comment indented more than the earlier parts?
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Don't add a bunch of commented out code.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
There probably should be, but Korey is the expert and would know for sure.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
I'm pretty sure it's not.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Which hack is that?
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Wrong indentation.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Wrong indentation.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Bracket goes on previous line
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Bracket on previous line. Fix below as well.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Fixing these random bits of trailing whitespace is good, but it should be its own change since it doesn't have anything to do with what this change is doing.
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
If CacheUnitEvent isn't used and shouldn't be called, get rid of it. Ideally in a separate change preceding this one.
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src/cpu/inorder/resources/graduation_unit.cc (Diff revision 5) -
Bad indentation.
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src/cpu/inorder/resources/graduation_unit.cc (Diff revision 5) -
Bad indentation.
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src/cpu/inorder/resources/inorder_translation.hh (Diff revision 5) -
Don't comment out code, delete it.
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src/cpu/translation.hh (Diff revision 5) -
The indentation here is wrong, unless review board is confused somehow. Please fix up style problems.
Posted (April 3, 2012, 10:59 p.m.)
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src/cpu/inorder/resources/cache_unit.cc (Diff revision 5) -
Where does data come from?
Posted (April 4, 2012, 4:32 a.m.)
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configs/common/Simulation.py (Diff revision 6) -
Will remove this is next change ...
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src/cpu/inorder/inorder_dyn_inst.hh (Diff revision 6) -
This code compiles and runs for ALPHA-Hello World now. It needs to be run through the regressions before an update as well as get an update from the reviewers. Next up is adding micro-ops to InOrder and then...finally...it will be ARM-Compatible.
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src/cpu/translation.hh (Diff revision 6) -
Both ITB/DTB are using this so I am planning on deleting this assert...
Review request changed
Updated (Aug. 19, 2012, 4:28 p.m.)
Testing Done: |
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Review request changed
Updated (Aug. 27, 2012, 12:34 a.m.)
Testing Done: |
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