ARM: fix value of MISCREG_CTR returned by readMiscReg()
Review Request #1117 - Created March 31, 2012 and submitted
| Information | |
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| Tony Gutierrez | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 9087:920818736f19 --------------------------- ARM: fix value of MISCREG_CTR returned by readMiscReg() According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
Ran BBench with the mcr icimvau instruction implemented. There is kernel code that relies on the proper implementation of this register when performing cache maintenance operations see arch/arm/mm/cache-v7.S in the linux kernel source.
Review request changed
Updated (March 31, 2012, 2:05 a.m.)
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Review request changed
Updated (July 3, 2012, 7:41 a.m.)
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Revision 2 (+37 -2) |
Review request changed
Updated (July 3, 2012, 7:51 a.m.)
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Revision 3 (+38 -2) |
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