src/mem/packet.hh (Diff revision 1)

it's not used, but we probably need to bring this back. The current implementation isn't great either and needs some help.

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1. Andreas Hansson May 2, 2012, 3:41 a.m. (May 2, 2012, 3:41 a.m.)

   Is this not covered by the more detailed attributes: IsSWPrefetch and IsHWPrefetch (line 139 and 140 in packet.hh)?

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src/mem/packet.hh (Diff revision 1)

This transaction used to be used by the DMA engine when writing full blocks to memory (see http://repo.gem5.org/gem5/rev/4ac3d9486d6e).

I see it's not used anymore since we put the I/O cache in place to deal with partial block writes (see http://repo.gem5.org/gem5/rev/ad0e792a5c78).

I don't see anything in the cache code that treats full-block writes specially (other than writebacks, which are different because in that case the requester already had exclusive access).

Does this mean the I/O cache is doing read-exclusive operations on every full-cache-block DMA?  That seems bad.

In other words, instead of getting rid of WriteInvalidateReq because it's not used, should we be trying to use it again?

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src/mem/packet.hh (Diff revision 1)

hrm.. I think we probably want to do full block writes with writeinvrequest. 

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1. Andreas Hansson May 9, 2012, 6:45 p.m. (May 9, 2012, 6:45 p.m.)

   I am perfectly fine with not removing it if it is indeed used, the question is who wants to change the DMA to use it again, and when? 
   
   (I don't know the cache models well enough to feel comfortable in making this type of change at the moment.)
   
   Any volunteers?

2. Andreas Hansson May 21, 2012, 3:10 a.m. (May 21, 2012, 3:10 a.m.)

   Is the conclusion that this can be removed (for clarity) and if anyone at any point wants to enhance the functionality they can add it again?

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