Adding a cpu model named simpleEdgeCPU to support EDGE style execution. Most of these codes are borrowed from O3. There're some outstanding features:
1) 4-stage model including fetch, map, execute and commit, to target on modeling the common characteristics of EDGE.
2) Adding a class named edgeBlock to hold information of an EDGE inst block. Right now it is mainly for the TRIPS inst block.
3) Fetch will fetch instructions and form inst blocks.
4) Map is planned to implement some dynamic mapping algorithms but right it's just a dummy stage.
5) Execute will execute inst in EDGE style, say, waking dependent insts directly without renaming.
6) Commit will commit in granularity of inst blocks.

This model with TRIPS ISA support can run SPEC CPU2000 using test input set.

build cmd lines:

% scons CPU_MODELS=simpleEdgeCPU build/TRIPS_SE/m5.debug