Regression: Use addTwoLevelCacheHierarchy in configs
Review Request #1450 - Created Sept. 26, 2012 and submitted - Latest diff uploaded
| Information | |
|---|---|
| Andreas Hansson | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
changesets: 9272:53a03371470f "Regression: Use addTwoLevelCacheHierarchy in configs This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween. The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock. The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache."
util/regress all passing (disregarding t1000 and eio)
