Regression: Use CPU clock and 32-byte width for L1-L2 bus

Information
Submitter:	Andreas Hansson
Repository:	gem5
Branch:	default
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Description

Changeset 9284:629583c5f1d5
---------------------------
Regression: Use CPU clock and 32-byte width for L1-L2 bus

This patch changes the CoherentBus between the L1s and L2 to use the
CPU clock and also four times the width compared to the default
bus. The parameters are not intending to fit every single scenario,
but rather serve as a better startingpoint than what we previously
had.

Note that the scripts that do not use the addTwoLevelCacheHiearchy are
not affected by this change.

A separate patch will update the stats.

Testing Done

util/regress all passing (disregarding t1000 and eio)

Any objections or good to go?

Andreas Hansson Oct. 10, 2012, 10:30 p.m. (Oct. 10, 2012, 10:30 p.m.)

I changed to 32 bytes on Ali's suggestion. This is probably on the wider side for ARM systems, and there are recent Intel systems that hit 64 bytes, but 32 should be a good starting point. 

Do everyone agree with the current defaults?

Summary:

-	Regression: Use CPU clock and 16-byte width for L1-L2 bus
+	Regression: Use CPU clock and 32-byte width for L1-L2 bus

Description:

		changesets:
~		9274:567811d0ebdc "Regression: Use CPU clock and 16-byte width for L1-L2 bus
	~	9283:4d24df0f5278 "Regression: Use CPU clock and 32-byte width for L1-L2 bus

		This patch changes the CoherentBus between the L1s and L2 to use the
~		CPU clock and also double the width compared to the default bus. The
~		parameters are not intending to fit every single scenario, but rather
~		serve as a better startingpoint than what we previously had.
	~	CPU clock and also four times the width compared to the default
	~	bus. The parameters are not intending to fit every single scenario,
	~	but rather serve as a better startingpoint than what we previously
	+	had.

		Note that the scripts that do not use the addTwoLevelCacheHiearchy are
		not affected by this change.

		A separate patch will update the stats."

Diff:

Revision 2 (+4 -1)

Show changes

src/cpu/BaseCPU.py

Description:

~		changesets:
~		9283:4d24df0f5278 "Regression: Use CPU clock and 32-byte width for L1-L2 bus
	~	Changeset 9284:629583c5f1d5
	~
	+	Regression: Use CPU clock and 32-byte width for L1-L2 bus

		This patch changes the CoherentBus between the L1s and L2 to use the
		CPU clock and also four times the width compared to the default
		bus. The parameters are not intending to fit every single scenario,
		but rather serve as a better startingpoint than what we previously
		had.

		Note that the scripts that do not use the addTwoLevelCacheHiearchy are
		not affected by this change.

~		A separate patch will update the stats."
	~	A separate patch will update the stats.

Diff:

Revision 3 (+23 -10)

Show changes

	configs/common/CacheConfig.py
	src/cpu/BaseCPU.py

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Description:

Changeset 9284:629583c5f1d5

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Status: Closed (submitted)