mem: Make LL/SC locks fine grained
Review Request #1540 - Created Nov. 20, 2012 and submitted
| Information | |
|---|---|
| Mitch Hayenga | |
| gem5 | |
| Reviewers | |
| Default | |
The current implementation in gem5 just keeps a list of locks per cacheline. Due to this, a store to a non-overlapping portion of the cacheline can cause an LL/SC pair to fail. This patch simply adds an address range to the lock structure, so that the lock is only invalidated if the store overlaps the lock range.
Have been using it myself for a few weeks on mostly SE, single-threaded code. Have also run the quick regressions, the o3-timing regressions "fail" simply because the stats differ (fewer LL/SC pairs executed, because they are now succeeding on their first try).
Posted (Nov. 23, 2012, 5 a.m.)
Looks good to me. Is the default parameter for request necessary?
Posted (Nov. 25, 2012, 8:18 a.m.)
Do we know if any of the processors actually keep a list of locks per cache line?
Ship It!
