x86 isa: This patch attempts an implementation at mwait.
Review Request #1622 - Created Jan. 14, 2013 and submitted
| Information | |
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| Derek Hower | |
| gem5 | |
| default | |
| Reviewers | |
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Changeset 9468:1712e13b7a5d --------------------------- x86 isa: This patch attempts an implementation at mwait. This patch takes advantage of the fact that Ruby protocols forward cache line evictions to the CPU to keep the LSQ in the O3 CPU consistent. Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Notes: 1. This implementation only works with ruby. 2. It has not been tested with the O3 cpu. 3. This patch was created by Marc Orr (morr@cs.wisc.edu)
Issue Summary
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| Description | From | Last Updated | Status |
|---|---|---|---|
| This won't work with FS mode. Actually I think it will crash | Ali Saidi | Jan. 14, 2013, 3:07 a.m. | Open |
| What if the system isn't a ruby system, or a ruby system doesn't exist? | Ali Saidi | Jan. 14, 2013, 3:07 a.m. | Open |
| This code is only required for the O3 CPU, if you haven't tested it are you comfortable adding it to ... | Ali Saidi | Jan. 14, 2013, 3:07 a.m. | Open |
| Perhaps if the cpu is x86? I'm not sure we want to slow the sytem down by processing snoops in ... | Ali Saidi | Jan. 14, 2013, 3:07 a.m. | Open |
| same as atomic | Ali Saidi | Jan. 14, 2013, 3:07 a.m. | Open |
| Perhaps a isa traits so that this can be skipped entirely in other isas? | Ali Saidi | Jan. 14, 2013, 3:07 a.m. | Open |
Posted (Jan. 14, 2013, 3:07 a.m.)
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src/cpu/base.cc (Diff revision 1) -
This won't work with FS mode. Actually I think it will crash
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src/cpu/base.cc (Diff revision 1) -
What if the system isn't a ruby system, or a ruby system doesn't exist?
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src/cpu/base_dyn_inst.hh (Diff revision 1) -
This code is only required for the O3 CPU, if you haven't tested it are you comfortable adding it to the repository?
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src/cpu/simple/atomic.hh (Diff revision 1) -
Perhaps if the cpu is x86? I'm not sure we want to slow the sytem down by processing snoops in the simple cpu if we don't need to
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src/cpu/simple/timing.hh (Diff revision 1) -
same as atomic
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src/cpu/simple/timing.cc (Diff revision 1) -
Perhaps a isa traits so that this can be skipped entirely in other isas?
Review request changed
Updated (Jan. 25, 2013, 6:15 a.m.)
Change Summary:
Updates from Marc: 1. I've tested and confirmed that this version works with all CPU models (including O3), and in both syscall emulation and full system. 2. I ran into minor issues testing the O3 in syscall emulation where I was running out of stack space. I think there is a bug somewhere in the simulator (or more likely m5threads), but I was able to hack around it for testing purposes. This issue is orthogonal to this patch, so I hope to not worry about it for now. 3. While mwait does work in full system, testing it was a nightmare. This is because interrupts from a hardware timer and system calls trigger wakeups frequently. In fact, wakeups are triggered so frequently, that I suspect something may be wrong with fully system mode (maybe the timer is not running at the correct speed?). Again, this potential issue is orthogonal to this patch.
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Revision 2 (+328 -16) |
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Posted (Feb. 8, 2013, 8:14 a.m.)
Marc, in your update you have mentioned that there might be problems with some of the parts of gem5. I suggest that you post the details of the problems to gem5-dev list, especially how those problems can be reproduced. No one may tackle those bugs in the near future, but it might be helpful to know that these bugs exist.