ARM: Implement some more misc registers

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Submitter:	Ali Saidi
Repository:	gem5
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Description

ARM: Implement some more misc registers

Testing Done

src/arch/arm/isa.cc (Diff revision 1)

These should probably be initialized in isa.cc and then just read normally. Writes would then be ignored.

src/arch/arm/miscregs.hh (Diff revision 1)

Why move this and not the other MISCREG_ID_MMFR*? Why move this one at all? Why move ACTLR?

src/arch/arm/miscregs.hh (Diff revision 1)

Because they need to be implemented and the others do not.

Gabe Black Aug. 14, 2010, 7:25 a.m. (Aug. 14, 2010, 7:25 a.m.)

I don't see why that matters. If they need to be implemented, that's taken care of separately in a different file and shouldn't be a consideration here.

src/arch/arm/isa.cc (Diff revision 1)

I don't see why that's any better. The warns are there because I intend to implement some functionality for them at some point, but I haven't gotten around to doing it. I would both like to be reminded of this fact on access and like to get past this point at present.

Gabe Black Aug. 17, 2010, 8 a.m. (Aug. 17, 2010, 8 a.m.)

I think we're talking about different things. I'm talking about the ones that already return something, not the ones that are warning below that. The warning ones are fine.

src/arch/arm/miscregs.hh (Diff revision 1)

It matters because they must be moved above MISCREG_CP15_UNIMP_START to not cause a panic() when they are accessed because they're unimplemented.

Gabe Black Aug. 17, 2010, 8 a.m. (Aug. 17, 2010, 8 a.m.)
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You're right, I'd forgotten about that. Never mind!
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