mem: Make packet bus-related time accounting relative
Review Request #1712 - Created Feb. 13, 2013 and submitted
| Information | |
|---|---|
| Andreas Hansson | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 9518:ddeec93f45f8 --------------------------- mem: Make packet bus-related time accounting relative This patch changes the bus-related time accounting done in the packet to be relative. Besides making it easier to align the cache timing to cache clock cycles, it also makes it possible to create a Last-Level Cache (LLC) directly to a memory controller without a bus inbetween. The bus is unique in that it does not ever make the packets wait to reflect the time spent forwarding them. Instead, the cache is currently responsible for making the packets wait. Thus, the bus annotates the packets with the time needed for the first word to appear, and also the last word. The cache then delays the packets in its queues before passing them on. It is worth noting that every object attached to a bus (devices, memories, bridges, etc) should be doing this if we opt for keeping this way of accounting for the bus timing.
All regressions passing (excluding t1000 and eio)
Issue Summary
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| Description | From | Last Updated | Status |
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| Does it make sense to include this offset in the relative time between the header and the data words? If ... | Steve Reinhardt | Feb. 16, 2013, 3:52 a.m. | Open |
Posted (Feb. 16, 2013, 3:52 a.m.)
Thank you! It has always bothered me that we never really used this timing information properly. You probably figured this out already, but the idea here is that we don't want to always schedule multiple events for every data transfer, yet we need to enable devices like caches to properly model critical-word-first forwarding. Basically naive devices should use curTick()+pkt->busLastWordDelay as the effective packet arrival time, and only devices doing critical-word-first optimizations should care about doing anything based on curTick()+pkt->busFirstWordDelay. One alternative that might simplify other devices at the cost of making the bus a little more complicated would be for slaves to indicate whether they care about critical word first optimizations, and have the bus schedule transmission events either at pkt->busFirstWordDelay or at pkt->busLastWordDelay depending on the slave's indication. Then at least the average dumb slave will be more likely to get the timing right, though at the cost of making the port semantics even more confusing. If you have any other ideas on better ways to achieve this, I'm open to suggestions.
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src/mem/bus.cc (Diff revision 1) -
Does it make sense to include this offset in the relative time between the header and the data words? If so, I don't understand why...
Ship It!
